Page buffer for NAND flash memory

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C365S230010, C365S189050, C365S185250

Reexamination Certificate

active

07016229

ABSTRACT:
A page buffer for an NAND flash memory, including: a first latch for loading data; a second latch for storing data stored on a cell depending on a bit line selection signal; a setting circuit for setting the first latch to a high level to load data in a high level; a first switching circuit for transferring the data stored on the second latch depending on a data output signal of a page buffer; a discharging circuit for discharging charges on a data line; a second switching circuit for connecting the data line discharged by the discharging circuit to the first latch depending on a data control signal to load the data in a low level to the first latch; and a data transferring circuit for transferring the data of the first latch to the second latch.

REFERENCES:
patent: 6717857 (2004-04-01), Byeon et al.
patent: 6813184 (2004-11-01), Lee
patent: 6826082 (2004-11-01), Hwang et al.
patent: 2003/0117856 (2003-06-01), Lee et al.

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