Page buffer for multi-level NAND electrically-programmable...

Details Page buffer for multi-level NAND electrically-programmable... Page buffer for multi-level NAND electrically-programmable...

2007-06-21

2009-12-08

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S189050, C365S203000

Reexamination Certificate

active

07630238

ABSTRACT:
A page buffer for an electrically programmable memory is provided. The page buffer includes a plurality of memory cells, a plurality of distinct programming states defined for each memory cell, corresponding to a number N>=2 of data bits storable in each memory cell, wherein the data bits include at least a first data bits group and a second data bits group and at least one read/program unit having a coupling line operatively associable with selected memory cells.

REFERENCES:
patent: 5751634 (1998-05-01), Itoh
patent: 7336538 (2008-02-01), Crippa et al.
patent: 7359245 (2008-04-01), Kim et al.
patent: 2006/0104112 (2006-05-01), Hosono et al.
patent: 2008/0080260 (2008-04-01), Seong
Examination Report from European Patent Application No. 06115809.3 mailed Mar. 18, 2008, 5 pgs.
Further Examination Report from European Patent Application No. 06115809.3 mailed Dec. 5, 2008, 4 pgs.
European Search Report, EP06115809, Nov. 28, 2006.

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