Page buffer for a programmable memory device

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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C365S189050, C365S189120, C365S230080, C365S238500

Reexamination Certificate

active

11134158

ABSTRACT:
A page buffer is provided for an electrically programmable memory that includes multiple memory cells forming multiple memory pages. The page buffer includes a register for at least temporarily storing data read from or to be written to the memory cells of a selected memory page. The register includes multiple latches and multiple buffer elements. Each of the latches is coupled to at least one signal line for transferring the data bit that is stored in the latch. Each of the buffer elements decouples an output of a corresponding one of the latches from the signal line, with the buffer element driving the signal line according to the data bit stored in the corresponding latch. Also provided is a method of transferring data from a register to signal lines in an electrically programmable memory.

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Seungjae Lee et al., “A 3.3V 4Gb Four-Level NAND Flash Memory with 90nm CMOS Technology”, ISSCC 2004/Session 2 Non-Volatile Memory/2.7, IEEE International Solid-State Circuits Conference, 2004, XP010722148, ISBN: 0-7803-8267-6.
European search Report for Application EP 04 10 2232 Dated May 2, 2005.

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