Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2007-08-14
2007-08-14
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230080
Reexamination Certificate
active
11306073
ABSTRACT:
A page buffer circuit of a flash memory device includes page buffers which are connected to the plurality of bit line pairs, respectively, and execute a read operation or a program operation on memory cells in response to bit line control signals, bit line select signals and control signals, and bit line precharge circuits, which are connected to the plurality of bit line pairs, respectively, and in the read operation, precharge one of a pair of bit lines connected thereto to a reference voltage level in response to bit line precharge signals. The reference voltage can be a stable voltage regardless of variation in temperature and/or voltage. A bit line precharge circuit supplies a stable precharge voltage to bit line regardless of variation in temperature and/or voltage in a read operation. Therefore, erroneous data can be prevented from being read.
REFERENCES:
patent: 6704239 (2004-03-01), Cho et al.
patent: 6996014 (2006-02-01), Lee et al.
patent: 2003/0021172 (2003-01-01), Cho et al.
patent: 2005/0226046 (2005-10-01), Lee et al.
patent: 2005-063640 (2005-03-01), None
patent: 2000-0059746 (2000-10-01), None
patent: 10-2003-0072434 (2003-09-01), None
Hynix / Semiconductor Inc.
Le Vu A.
Marshall & Gerstein & Borun LLP
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