Page buffer and verify method of flash memory device using...

Details Page buffer and verify method of flash memory device using... Page buffer and verify method of flash memory device using...

2007-02-20

2007-02-20

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185120, C365S189050

Reexamination Certificate

active

11182152

ABSTRACT:
Disclosed herein are a page buffer and a verify method of a flash memory device where the page buffer of a dual register structure includes a switch, which is driven according to a voltage level of an input terminal of a main latch, to output an erase-verify signal, and a switch, which is driven according to a voltage level of an output terminal of the main latch, to output a program-verify signal. Program-verify and erase-verify operations are performed using only the main latch. The disclosed page buffer and verify method can reduce verification time relative to devices using both a cache latch and a main latch.

REFERENCES:
patent: 6999347 (2006-02-01), Mitani
patent: 1029940050697 (2004-06-01), None
Korean-language official action dated Mar. 22, 2006, issued by the Korean Intellectual Property Office in connection with the Korean priority application.

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