Page address translation cache replacement algorithm with improv

Details Page address translation cache replacement algorithm with improv Page address translation cache replacement algorithm with improv

1989-12-27

1992-10-13

Dixon, Joseph L.

Boots, shoes, and leggings

36424341, 364246, 36424612, 3642511, 364253, 364DIG1, 364DIG2, G06F 1212

Patent

active

051558254

ABSTRACT:
A replacement method is provided for improving the hit rate and testability of a page address translation cache (PATC). The replacement scheme uses a modified FIFO replacement algorithm. A circular shift register has a pointer which points to each of a predetermined number of translation descriptors stored in the PATC. The shift register pointer has an input for receiving the logic state of a valid bit associated with each of the translation descriptors stored in the PATC. The shift register is advanced after every translation cycle, until the logic state of the valid bit indicates that the denoted translation descriptor is invalid, or until a read/write control signal indicates a PATC write is in progress. Upon detecting an invalid translation descriptor, the circular shift register is disabled, and remains disabled until an address translation "miss" occurs, and a replacement entry is loaded into the PATC. If, however, an address translation miss occurs while the circular shift register is enabled (i.e. before an invalid descriptor is located, or when all descriptors are valid), then the translation descriptor the shift register points to is replaced by a new valid translation descriptor.

REFERENCES:
patent: 3806883 (1974-04-01), Weisbecker
patent: 4095283 (1978-06-01), Campbell et al.
patent: 4195343 (1980-03-01), Joyce
patent: 4562536 (1985-12-01), Keeley et al.
patent: 4783735 (1988-11-01), Miu et al.
patent: 4802086 (1989-01-01), Gay et al.
patent: 4928239 (1990-05-01), Baum et al.

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