Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means
Reexamination Certificate
1997-02-26
2001-10-16
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular power supply distribution means
C257S773000, C257S786000, C438S612000
Reexamination Certificate
active
06303948
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a semiconductor device and, more particularly, to a layout for pads and leads for a semiconductor device.
Generally, in a semiconductor device, pads for leading out electrodes from an internal circuit are arranged in a row along the periphery of the chip or in the central portion thereof.
FIGS. 1
to
3
show various examples of conventional pad layouts and lead layouts in which respective pads of the semiconductor chip are connected with the leads by wire bonding (in a state prior to the packaging).
FIG. 1
shows the layout which is most widely used and in which pads
12
are arranged along the four sides of the semiconductor chip
11
. The chip
11
is mounted on a bed B and the end portions of the leads
13
and the pads
12
are respectively connected via bonding wires
14
.
FIG. 2
shows the LOC (Lead On Chip) structure in which pads
12
are arranged along two opposite sides of a chip
11
and the end portions of leads
13
which are provided on the chip
11
are connected to the respective pads
12
via bonding wires
14
.
FIG. 3
shows the LOC structure of center pad type in which pads
12
are arranged in a row in the central portion of a chip
11
and the end portions of leads
13
which are provided on the chip
11
are connected to the respective pads
12
via bonding wires
14
.
The various types of pad layouts and lead layouts shown in
FIGS. 1
to
3
are described in Mitake et al., “Multi-byte 16 Mbit DRAM”, NEC Technical Report, Vol. 46, No. 2/1993, pages 94-97; U.S. Pat. No. 5,072,280 to Matsukura entitled “Resin Sealed Semiconductor Device”; and the article “Starting of Full-Scale Study of LOC for Second Generation 16 Mbit DRAM”, November 1991 issue of NIKKEI MICRODEVICES by NIKKEI BP Co., pages 79-83. Each of these documents is incorporated herein by reference.
Recently, with the development of LOC technology, even a small chip which is not required to use LOC is formed in an LOC configuration so as to permit LOC to be utilized. As a result, the pad area is made small. Further, due to diversification of applications, the number of pads has increased, thereby making it very difficult to attain a sufficiently large pad area on the chip. In a package in which pitches between the lead pins are small, it is necessary to make the pitches between the pads smaller, and the requirements for the pad layout and lead layout become increasingly severe.
In order to solve the above problems, a pad layout in which pads are arranged on plural rows as shown in
FIGS. 4 and 5
has been proposed. In
FIG. 4
, pads
12
-
1
,
12
-
2
are arranged in two rows in the central portion of a chip
11
, and in
FIG. 5
, pads
12
-
1
,
12
-
2
,
12
-
3
are arranged in three rows in the central portion of a chip
11
. By using the above pad layouts, it becomes easier to attain a sufficiently large pad area on the chip
11
and to reduce the length of the pad rows even if the number of pads increases. Thus, it becomes possible to cope with a reduction in chip size, an increase in the number of pads, and a reduction in pitch.
However, when the pads are arranged on plural rows, the following problems (a) to (f) occur. (a) Restrictions occur when the pads and the end portions of the leads are connected by wire bonding. (b) It is difficult to attain a sufficiently large distance between patterns of protection circuits provided for the pads. (c) A restriction is imposed on extensions of the wirings from the pads to the internal circuit. (d) It becomes difficult to arrange the power supply lines of the protection circuit. (e) It is necessary to apply probes to both sides of the chip when probes are applied to the chip in the wafer state and it is difficult to simultaneously test a plurality of chips. (f) Since bonding wires are formed at least on both sides of the chip, it becomes difficult to apply probes after wire bonding and it becomes difficult to measure the amplitudes of signals on signal lines and observe the signal waveforms at the time of development of new products.
That is, for example, in the pad layout shown in
FIG. 4
, since it is difficult to effect wire bonding if the leads are not formed to extend from the upper side and from the lower side of the chip
11
, it is difficult to apply the layout to a package such as SVP (Surface Vertical Package) and ZIP (Zigzag In-line Package) in which the leads are formed to extend from one side of the chip
11
. In addition, when pads are arranged in more than row, the number of chips which can be simultaneously tested decreases. For example, in the case in which pads are arranged in a single row, one chip (or the chips in a first row) can be tested by moving a first probe into contact with the wafer from a first direction and another chip (or the chips in a second row) can be tested by moving a second probe into contact with the wafer from a second direction opposite to the first direction. However, in the case in which pads are arranged in two rows, these two probes are needed for testing one chip (or the chips in one row). Thus, in the case in which pads are arranged in two rows, only half as many chips can be simultaneously tested as compared to the case in which pads are arranged in a single row. Further, when the bonding wires and leads are formed on both sides of the chip, it becomes difficult after a wire bonding step to move the probes in the first and second directions into contact with pads arranged in two rows. When an internal signal in the chip is measured, test signals or power is supplied to the chip via the leads formed on the side of the chip. In order to test the chip, the probes are moved into contact with the pads by being pushed through the leads which supply the test signals or power to the chip. It is therefore difficult to test the operating characteristics of the chip. Still further, as shown in
FIG. 6
, protection circuits
15
-
1
,
15
-
2
for protecting the internal circuits from surge voltages are disposed in position adjacent to the pads
12
-
1
,
12
-
2
. It is necessary to form the protection circuits
15
-
1
,
15
-
2
in a deep diffusion layer such as a well region and it is necessary to attain a sufficiently long minimum distance LA between the patterns of the protection circuits
15
-
1
and
15
-
2
formed adjacent to each other by taking the lateral diffusion of the diffusion layer into consideration. For this reason, the pad layout is limited by the patterns of the protection circuits
15
-
1
,
15
-
2
, thereby making it difficult to reduce the pitches between the pads
12
-
1
,
12
-
2
. When wirings are lead out from the protection circuits
15
-
1
,
15
-
2
to the internal circuit, the readout directions of the wirings
16
-
1
,
16
-
2
are restricted as shown in FIG.
7
and thus extension of the wirings to the internal circuit is restricted. Further, power supply lines are required for the protection circuits
15
-
1
,
15
-
2
. As shown in
FIG. 8
, for example, it is necessary to dispose main power supply lines
17
-
1
,
17
-
2
on both sides of the pads
12
-
1
,
12
-
2
in the two rows and dispose branch power supply lines
17
-l
a
,
17
-l
b
,
17
-l
c
and
17
-
2
a
,
17
-
2
b
,
17
-
2
c
which are divided from the main power supply lines
17
-
1
,
17
-
2
in a branch for the respective protection circuits
15
-
1
,
15
-
2
. As a result, the pattern layout of the power supply lines of the protection circuits
15
-
1
,
15
-
2
becomes complicated and the pattern occupancy area becomes large.
The various problems described above become more serious if the number of rows of pads is set to three as shown in FIG.
5
and become even more serious as the number of rows of pads becomes greater than three.
As described above, the pad layout and lead layout of conventional semiconductor devices make it extremely difficult to effectively cope with a reduction in chip size, an increase in the number of pins of a package, and a reduction in the pitch of the pads.
Further, if the pads are disposed on plural rows i
Koyanagi Masaru
Kudou Manami
Banner & Witcoff , Ltd.
Chaudhuri Olik
Kabushiki Kaisha Toshiba
Weiss Howard
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