Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Ball or nail head type contact – lead – or bond
Reexamination Certificate
2000-05-09
2002-08-06
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Ball or nail head type contact, lead, or bond
C257S737000, C257S780000
Reexamination Certificate
active
06429532
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a package structure for semiconductor integrated devices, and more particularly to a pad design for flip chip package of semiconductor integrated devices.
2. Description of the Related Art
The manufacture of an integrated circuit (IC) can be roughly divided into three separate stages: the manufacture of a silicon chip, the production of an integrated circuit on the silicon chip and the packaging of the silicon chip. Hence, the packaging of the silicon chip can be regarded as the final stage in the integrated circuit fabrication process. A conventional IC package is used to package a single chip. However, in order to increase the capacity of a memory package, for example, or to integrate silicon chips having different functions, many packages now contain two silicon chips.
In general, in an IC package having two silicon chips, the silicon chips are mounted on the upper and lower sides of the lead frame. However, if the circuit layout of the two silicon chips is the same, two pieces of identical DRAM chips are used to increase memory capacity, and the metal wires that connect the bonding pads on the silicon chips with the lead frame may have to cross over each other, leading to a certain degree of entanglement with each other. The bonding pads are also used as testing points for wafer testing. For connecting silicon chips to other devices, bumps are usually formed as connecting mediums on the bonding pads.
FIG. 1
is a schematic diagram showing a conventional package structure. In the figure, a silicon chip
100
having a bonding pad
102
is provided. Bump
104
is formed on the bonding pad
102
. There is a protection layer
106
formed over the chip
100
but no over the bonding pad
102
. After finishing the package structure, a final test must be performed to ensure that the semiconductor device is workable. The final test can be performed either before or after forming the bump
104
on the bonding pad
102
. However, if the final test is performed after bumping, a test probe
108
would directly contact the bump
104
. The acute probe
108
may damage the bump
104
. Furthermore, the acute probe
108
can not easily contact the global bump
104
, so over-kill doesn't occur during testing. Whereas, if the final test is performed before bumping, failure occuring between the bonding pad
102
and the bump
104
cannot be detected. Also, the test probe
108
would directly contact the bonding pad
102
and cause a probe mark on the bonding pad
102
, which affects reliability when forming the bump
108
.
SUMMARY OF THE INVENTION
The invention provides a pad design. A final test can be performed after bumping without damaging the bump on the bonding pad. The pad design of the invention provides an additional testing pad that is electrically connected to a conventional bonding pad and positioned beside the bonding pad. The conventional bonding pad is formed on a provided chip, and a bump is formed on the bonding pad. A final test is performed on the testing pad so that damage formed on the bump or on the bonding pad can be prevented.
According to the pad design of the invention, a conventional probe card used for testing still can be used without any modifications. Furthermore, the final test is performed on the testing pad so that no probe mark would be formed either on the bonding pad or on the bump. Since there is no bump formed on the testing pad, the test probe can easily touch the testing pad without over-kill.
REFERENCES:
patent: 5262719 (1993-11-01), Magdo
patent: 5684304 (1997-11-01), Smears
patent: 5793117 (1998-08-01), Shimada et al.
patent: 5834844 (1998-11-01), Akagawa et al.
patent: 5838023 (1998-11-01), Goel et al.
patent: 6013537 (2000-01-01), Kuchta
patent: 6153448 (2000-11-01), Takahashi et al.
Han Charlie
Ho Kai-Kuang
Clark Jasmine J B
J.C. Patents
United Microelectronics Corp.
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