Pad arrangement in semiconductor memory device and method of...

Details Pad arrangement in semiconductor memory device and method of... Pad arrangement in semiconductor memory device and method of...

2007-04-03

2007-04-03

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S191000, C365S189040

Reexamination Certificate

active

10895554

ABSTRACT:
A semiconductor memory device comprising control pads and input/output I/O pads capable of reducing the data path for reading and writing data in a cell array, and a method for driving the semiconductor memory device are included. The semiconductor memory device comprises a plurality of memory banks arranged at a cell region of a memory chip, and a plurality of control pads and a plurality of I/O pads, separately arranged from each other at the memory chip, for reading/writing data from/in the memory banks, wherein the plurality of control pads and I/O pads are dispersed at the peripheral region between adjacent memory banks and at the outer portions of the memory banks.

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