Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1999-10-26
2001-10-09
Chin, Wellington (Department: 2664)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S386000
Reexamination Certificate
active
06301247
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally concerns the physical and electrical connection of (i) flat multiconductor cables, normally in the form of flexible printed circuit cables, to (ii) planar modules, or tiles, particularly modules in which reside both switching chips and printed wiring that constitute a portion of the interconnection paths of three-dimensional multi-stage interconnection, or switching, networks, a remaining portion of the switching network's interconnection paths being constituted by the flexible printed circuit cables.
The present invention particularly concerns the dense physical and electrical connection of (i) large numbers of flat flexible printed circuit cables, to (ii) to spaced-parallel planar switching modules so as to implement large, and very large, scale interconnection, or switching, networks.
2. Description of the Prior Art
The present invention is concerned with the physical realization of multi-stage interconnection switching networks which provide for the efficient and rapid communication of data between large numbers of electronic devices, typically hundreds and even thousands of computer data processors. The multi-stage interconnection switching networks involve (i) large numbers of semiconductor switch dice located in (ii) spaced-parallel planar modules which comprise the switching stages, and (iii) associated electrical interconnection wiring between the planar-arrayed dice in each stage, forming thus a switching network in three dimensions.
The switching networks of the present invention are designed with switches, or switchpoints, that are located in logical rows and in logical columns, as is common. Such switching networks are commonly physically constructed with the physical switches—which are commonly implemented from semiconductor dice—that are arranged into physical ranks and physical files. When large numbers of electronic devices must be interconnected by even larger numbers of switches, the switches are commonly logically and physically arrayed as multiple stages. Because laying out each of the stages on the same plane soon becomes unwieldy large, each stage is laid out on a single plane, and the planes are stacked one atop another in three dimensions.
If, for smaller switching networks, all the switches, or switchpoints, are physically located in a common plane—such as on a single circuit panel or on a number of circuit panels adjacent to one another, then the interconnection wiring between the outputs and the inputs of the various switches of this circuit panel may clearly be accomplished in, or substantially in, the plane of the circuit panel. When several circuit panels are used, it is common to connect from one to the next by edge connectors. The several printed circuit panels may be located in a single plane, and the edge connections may thus also be in this plane. However, if the edge connections are made with flexible cable, including the multiconductor flexible flat cable commonly know as ribbon cable, as is common, then the panels may usefully be arrayed spaced-parallel to each other in a stack.
Although wiring has occasionally been made from central areal regions of one panel directly across to corresponding central areal regions of an adjacent parallel panel, at last two problems have beset making electrical connection directly from one panel to another in the volume between them while attempting to realize high density, and minimal communication delay, within a multi-stage switching network. If the interconnecting wires are permanently, or semi-permanently, affixed to the panels, such as by soldering the wire ends in vias in the panels, then the successive panels must be “laid up” in order during construction, and become effectively impossible to disassemble for maintenance, including so as to replace any chip switches (located on the panels) that have failed.
If the interconnecting wires—commonly in the form of printed circuit multiconductor, or ribbon, cables with exposed conductor/wire ends—are not to be placed into vias within the panels and soldered, then a reliable form of electrical connection, and electrical connector, is needed between the interconnecting wires and the transverse panels. Moreover, even if a suitable connector is found, the typically high wiring density between the panels tends to turn the volume between the panels into a “rat's nest”, with physical conflicts between wires forcing the panels to greater separation and the interconnecting wires to greater lengths, and with an associated communications signal delay that is greater than would desirably be the case.
These problems have heretofore been so severe that free-space optical interconnections have been contemplated between panels of a stack for appreciably-sized multi-level switching network cross-connecting 256 nodes or more. Photons, being bosons, pass though each other in free space without appreciable cross-interference, and have thus been hypothesized to be more suitable for three-dimensional spatial-point to spatial-point communicative interconnection than are electrons, which, as fermions, strongly interfere with each other—whether or not carried on wires which. themselves exhibit spatial impermeability. Although there may yet be a point where three-dimensional optical interconnection, with all its overhead of transformation from and to the electrical signals presently used for computation and switching, becomes useful and even dominant, the present invention will be seen to concern good “old fashioned” point-to-point wiring, extending such wiring into multi-level networks of sizes heretofore believed highly impracticable, if not impossible, of being implemented by purely electrical connection.
The present invention will shortly been seen to contemplate a truly three-dimensional switching network where communication connections are made in the volume between adjacent parallel circuit panels, and along routes between panels which routes are transverse to the planes of the panels. In accordance with the present invention, the wiring between adjacent panels, although extremely dense and spatially sophisticated, is highly regular, and substantially devoid of spatial conflicts. In accordance with the second related invention, regular and reliable electrical connection may be made from the flat wiring circuits, or flexible printed circuit cables, located between adjacent panels and in planes transverse to the panels. Switching circuits are located in electrical dice upon, and co-planar with, the panels.
The three-dimensional switching network physical geometries of the present invention are suitable to implement diverse logical switching networks. Various prior art baseline switching networks, the reverse Banyan network, the Cantor network, the two-planed layered network, and many other of the layered networks that are described in U.S. Pat. No. 4,833,468 entitled LAYERED NETWORK, and which issued in the names of selected inventors of the present invention on May 23, 1989, are all examples of networks which may beneficially use the three-dimensional interconnection geometries of present invention.
However, the preferred wiring rules, patterns and topology of the present invention—i.e. the locations of the interconnection wires between the panel-mounted switches—are based upon “something” having been “done” with the layout of the selected logical switching network. What this “something” is that is “done” is taught within the first and second related patent applications. What is “done” in the layout of a switching network follows detailed rules, but is not too difficult to understand. Just why anything should be “done” and any rules should be followed—to make realizable an efficient physical geometry—will become increasingly clear when the results achievable by the design methodology, and by the present inventions, are explained in the present specification disclosure.
Although distinctly not part of the prior art—as the logical switching networks themselves are—the inventions of
Kryzak Charles
Larson Brian Ralph
Bowen Glenn W.
Chin Wellington
Hogan Patrick M.
Jones Prenell
Lockheed Martin Corporation
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