Packetized data transmissions in a switched router architecture

Details Packetized data transmissions in a switched router architecture Packetized data transmissions in a switched router architecture

1997-01-09

2001-08-28

Nguyen, Chau (Department: 2663)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S465000, C370S401000

Reexamination Certificate

active

06282195

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to a methodology and mechanism for efficiently processing packetized data in a switched routing scheme. In particular, the present invention pertains to a specialized set of functions, formats, and commands used to realize the full potential of packetized routing.
BACKGROUND OF THE INVENTION
In the past, computers were primarily applied to processing rather mundane, repetitive numerical and/or textual tasks involving number-crunching, spread sheeting, and word processing. These simple tasks merely entailed entering data from a keyboard, processing the data according to some computer program, and then displaying the resulting text or numbers on a computer monitor and perhaps later storing these results in a magnetic disk drive. However, today's computer systems are much more advanced, versatile, and sophisticated. Especially since the advent of multimedia applications and the Internet, computers are now commonly called upon to accept and process data from a wide variety of different formats ranging from audio to video and even realistic computer-generated three-dimensional graphic images. A partial list of applications involving these multimedia applications include the generation of special effects for movies, computer animation, real-time simulations, video teleconferencing, Internet-related applications, computer games, telecommuting, virtual reality, high-speed databases, real-time interactive simulations, medical diagnostic imaging, etc.
The reason behind the proliferation of multimedia applications is due to the fact that much more information can be conveyed and readily comprehended with pictures and sounds rather than with text or numbers. Video, audio, and three-dimensional graphics render a computer system more user friendly, dynamic, and realistic. However, the added degree of complexity for the design of new generations of computer systems necessary for processing these multimedia applications is tremendous. The ability of handling digitized audio, video, and graphics requires that vast amounts of data be processed at extremely fast speeds. An incredible amount of data must be processed every second in order to produce smooth, fluid, and realistic full-motion displays on a computer screen. Additional speed and processing power is needed in order to provide the computer system with high-fidelity stereo, real-time, and interactive capabilities. Otherwise, if the computer system is too slow to handle the requisite amount of data, its rendered images would tend to be small, gritty and otherwise blurry. Furthermore, movement in these images would likely be jerky and disjointed because its update rate is too slow. Sometimes, entire video frames might be dropped. Hence, speed is of the essence in designing modern, state-of-the-art computer systems. Furthermore, although some applications can tolerate a small degree of delay, other applications must have an absolute amount of given bandwidth. In other words, certain video applications need to always be guaranteed bandwidth to ensure that it is processed properly. For instance, it is critical for computerized video produced for national television broadcast to be guaranteed the minimum amount of bandwidth for processing. Otherwise, glitches might occur in the middle of a program or show.
One of the major bottlenecks in attaining faster, greater bandwidth computer systems pertains to the prior art bus architecture. A “bus” is comprised of a set of wires that is used to electrically interconnect the various semiconductor chips and input/output devices of the computer system. Electric signals are conducted over the bus so that the various components can communicate with each other. The major drawback to this prior art bus architecture is the fact that it is a “shared” arrangement. All of the components share a common bus. They all rely on a single bus to meet their individual communication needs. However, the bus can only establish communications between two devices at any given time. Hence, if the bus is currently busy transmitting signals between two of the devices, then all the other devices coupled to that bus must wait their turn until that transaction is complete and the bus again becomes available. If a conflict arises, an arbitration circuit resolves which of the devices gets priority. Essentially, the bus is analogous to a telephone “party” line, whereby only one conversation can take place amongst a host of different handsets serviced by the party line. If the party line is currently busy, one must wait until the prior parties hang up, before one can initiate their own call.
In the past, this type of bus architecture offered a simple, efficient, and cost-effective method of transmitting data. For a time, it was also sufficient to handle the trickle of data flowing between the various devices residing within the computer system. However, as the demand for increased amounts of data skyrocket, designers have to find ways to improve the speed at which bits of data can be conveyed (i.e., increased bandwidth) over the bus. One such solution is to implement a switching matrix as described in the patent application entitled “Packet Switched Router Architecture For Providing Multiple Simultaneous Communications,” Ser. No. 08/717580, filed on Sep. 23, 1996, and assigned to the assignees of the present invention. Rather than having a shared bus arrangement, a central “switchboard” arrangement is used to select and establish temporary links between multiple devices. In this manner, multiple links can be established between any number of components. In order to transmit data more efficiently within the scope of this new bus architecture, data is divided and transmitted in the form of “packets.” These packets are then sent over the links. By selecting and establishing multiple links, the central switchboard allows multiple packets to be sent to various destinations. This results in significantly greater bandwidth because multiple high-speed packetized transmissions can occur simultaneously. In addition, such a packetized router architecture facilitates the implementation of a guaranteed bandwidth scheme (see patent application entitled “A Guaranteed Bandwidth Method In A Computer System For Input/Output Data Transfers,” Ser. No. 08/717581, filed on Sep. 20, 1996, and assigned to the assignees of the present invention).
With the basic architecture and protocol established, there yet remains other unique, novel features which can be leveraged to gain even greater performance characteristics. Hence, the present invention pertains to the methodology and mechanism for facilitating the most efficient and advantageous handling of packetized data in a switched routing scheme. In particular, the present invention pertains to a specialized set of functions, formats, and commands used to capture the full potential of packetized routing.
SUMMARY OF THE INVENTION
The present invention pertains to a switched router for transmitting packetized data concurrently between a plurality of devices coupled to the switched router. Various devices or chips within a computer system are coupled to the I/O ports of the switched router. The switched router is then programmed to route packets of data from various source ports to the appropriate destination ports. Different packets may be transmitted concurrently between two or more devices through the switched router. The packets are comprised of a command word containing information specifying packet routing, data format, size, and transaction identification. Furthermore, the command word may include a destination identification number for routing the packet to a destination device, a source identification number used by a destination device to send back responses, a transaction number to tag requests that require a response, and a packet type value indicating a particular type of packet. In addition, there may be bits within a packet used to indicate a coherent transaction, guarantee bandwidth flag an error during transmission, or indicate a sync ba

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