Computer graphics processing and selective visual display system – Computer graphic processing system – Graphic command processing
Reexamination Certificate
1999-11-23
2001-12-18
Bayerl, Raymond J. (Department: 2773)
Computer graphics processing and selective visual display system
Computer graphic processing system
Graphic command processing
C345S541000, C345S542000, C345S553000, C345S556000
Reexamination Certificate
active
06331857
ABSTRACT:
RELATED APPLICATIONS
The following co-pending patent application is related to the subject application and is herein incorporated by reference:
U.S. application Ser. No. 08/713,779, now U.S. Pat. No. 6,104,417, filed Sep. 15, 1996, entitled “A Unified Memory Computer Architecture With Dynamic Graphics Memory Allocation” of Michael K Nielsen and Zahid S. Hussain.
FIELD OF THE INVENTION
The present invention relates generally to systems for computer graphics. More specifically, the present invention includes a method for passing commands to a graphics processor.
BACKGROUND OF THE INVENTION
Modern, computers (and related devices) typically produce graphical output using a sequence of tasks known as a graphics pipeline. These tasks start with a mathematical representation of an image to be produced and finish with pixel data suitable for display on a video screen or other output device. The tasks that perform this translation (i.e., the tasks included in a graphics pipeline) may be performed entirely by the host processor or processors included in a host computer system. Another common arrangement is to split the graphics pipeline so that the host processor performs only an initial subset of the pipeline tasks. The remaining tasks are then performed by a specialized graphics processor. Splitting the graphics pipeline often results in increased graphics throughput (due to the specialized abilities of the graphics processor). Splitting also generally results in increased throughput for the host processor (due to the decreased demands placed on the host processor).
In architectures where graphics processors are used, the initial subset of pipeline tasks are typically performed as part of user-mode, non-privileged, execution of the host processor. This means that these tasks may be included within a user process or application. It also means that these tasks may be replicated within a series of processes. Effectively, the graphics pipeline is modified so that a group of initial pipeline segments are all multiplexed to feed the graphics processor.
Use of a graphics processor also means that the output of the initial pipeline segment, or segments, must be transferred to become the input of the graphics processor. In an ideal architecture, this transfer would be accomplished at little or no cost. Unfortunately, in traditional architectures, access to the graphics processor cannot be accomplished as part of user-mode execution of the host processor. Instead, a user process or application that desires to send information to the host processor must do so as part of a system call. The system call invokes the operating system of the host processor and the operating system performs the transfer on behalf of the user process. The context switch from user-mode to privileged mode is time consuming and decreases the efficiency of the graphics process.
In addition to being time consuming, the use of a system call also tends to serialize the operation of the host and graphics processor. This follows because the use of a system call forces the operating system to act as a sort of arbitrator between the host and graphics processors. If the graphics processor finishes its current tasks, it is forced to wait until the operating system decides to transfer more work to the graphics processor. If the operating system is attending to other duties, available work may have to wait to be transferred. Thus, the host and graphics processors exhibit an unnecessary degree of interdependence and potential parallism remains un-exploited.
SUMMARY OF THE INVENTION
The present invention includes a method and apparatus for efficiently transferring graphics commands to a graphic processor. A representative environment for the present invention includes a host computer system having one or more host processors and a graphics processor. The host computer also includes a system memory. The system memory is addressable by the host and graphics processors.
The host computer system provides an environment for the production of computer graphics. Within this environment, graphics processes are associated with rendering contexts. Each rendering context provides a virtual interface to the graphic processor. As part of this interface, each rendering context includes one or more rendering packets. Each rendering packet is a data structure that includes a packet buffer and an associated packet descriptor. A packet buffer is a memory region into which graphics commands may be stored. The size of each packet buffer (and thus, the number of graphics commands that may be stored in the packet buffer) may be varied to suit the needs of a particular embodiment of the present invention. A packet descriptor is a compact data structure that, for the described embodiment, includes a ready variable, an interrupt variable, a size variable and a next pointer. The size variable of a rendering packet is initialized to contain the number of memory words included in the packet buffer of the rendering packet. Upon initialization, the ready variable and the interrupt variable are both set to false.
The next pointer is used to form linked lists, or queues, of rendering packets. For one arrangement, the rendering packets in each graphics context are linked into one or more circular queues. For another arrangement, all of the rendering packets included in the host computer system are linked into a circular queue. Still other arrangements are practical and advantageous for particular environments and applications.
To send commands to the graphics processor, a graphics process first selects a rendering packet. The ready variable included in the selected rendering packet must be set to a value of false. If the selected rendering packet does not have a false ready variable, the graphics process either waits or performs other processing. When the graphics process determines that the ready variable of the selected rendering packet is false, the graphics process batches graphics commands to the packet buffer. The graphics process then sets the ready variable included in the selected rendering packet to a value of true. Setting the ready variable to true indicates that the rendering packet is ready for processing by the graphics processor.
The graphics processor traverses the queues of rendering packets. At each rendering packet, the graphics processor polls the state of the ready variable. When this variable is set to true, the graphics processor executes each of the commands included in the packet buffer of the rendering packet. Once execution of these commands is complete, the graphics processor sets the ready variable to false. If the interrupt variable is set to true, the graphics processor then sends an interrupt signal to the host processor.
As may be appreciated, the present invention provides a method and apparatus that allow the host and graphics processors to function in a relatively independent, asynchronous manner. Additionally, transfer of commands to the graphics processor occurs as part of user-mode execution of the host computer system without the need for a system call.
Advantages of the invention will be set forth, in part, in the description that follows and, in part, will be understood by those skilled in the art from the description herein. The advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims and equivalents.
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Hussain Zahid S.
Millet Timothy J.
Bayerl Raymond J.
Luu Sy D.
Silicon Graphics Incorporated
Squire Sanders & Dempsey L.L.P.
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