Packet video signal inverse transport processor memory address c

Details Packet video signal inverse transport processor memory address c Packet video signal inverse transport processor memory address c

1995-09-13

1997-03-18

Cain, David C.

Cryptography

Particular algorithmic function encoding

Nbs/des algorithm

348384, 348441, 348348, H04N 7167

Patent

active

056130031

ABSTRACT:
In an inverse transport processor, program component packet payloads of respective program components are multiplexed to a memory data input port and directed to mutually exclusive areas of random access memory (RAM). The processor includes multiple direct memory access circuitry for writing the payloads of component data to the mutually exclusive blocks of the memory. Memory access for read and write functions are arbitrated so that no incoming program data can be lost, and all component processors are serviced.

REFERENCES:
patent: 4823201 (1989-04-01), Simon et al.
patent: 5038346 (1991-06-01), Courtois
patent: 5168356 (1992-12-01), Acampora et al.
patent: 5233654 (1993-08-01), Harvey et al.
patent: 5289276 (1994-02-01), Siracusa et al.

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