Packet transmission/reception processor

Details Packet transmission/reception processor Packet transmission/reception processor

2005-12-20

2005-12-20

Phan, Man U. (Department: 2665)

Multiplex communications

Diagnostic testing

Fault detection

C370S389000, C370S412000, C709S250000

Reexamination Certificate

active

06977901

ABSTRACT:
If a packet processing controller at a consumer node has failed to process a received packet within a predetermined amount of time, a packet processing control timer detects a time-out and informs a CPU of that. In response, the CPU issues packet processing suspend instruction and packet transmit instruction for the controller by way of a register. In accordance with these instructions, the controller suspends the current packet processing and produces header and data for a WRS packet, which is transmitted to a producer node through a bus. In this manner, a packet can be processed without causing a time-out at the producer node.

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