Multiplex communications – Communication techniques for information carried in plural... – Assembly or disassembly of messages having address headers
Reexamination Certificate
2001-02-01
2004-09-14
Vanderpuye, Kenneth (Department: 2661)
Multiplex communications
Communication techniques for information carried in plural...
Assembly or disassembly of messages having address headers
C370S395100
Reexamination Certificate
active
06792002
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a packet transfer system for assembling logically multiplexed ATM (Asynchronous Transfer Mode) cells into a packet and for transmitting the packet to a destination logical channel according to packet header information. More particularly, the present invention relates to a packet transfer system adapted to separate and couple a transfer performed by hardware processing and a transfer performed by software processing.
In recent years, a demand for increasing the packet transfer rate of a packet transfer system has occurred with the increase in packet traffic in an ATM network that transfers an IP (Internet Protocol) packets. Implementation of a packet transfer process consisting of a series of steps of assembling a packet, retrieving transfer destination information, and transmitting a packet by hardware has been promoted to ensure the demand. On the other hand, concurrently, there has been an increase in traffic of high-level protocol packets requiring the implementation of a packet transfer process by software. Thus, there has been a demand for enhancement of the throughput of the packet transfer process implemented by software, in addition to the demand for increasing the packet transfer rate by the implementation of the packet transfer process by hardware.
Consequently, there is a need for providing a coupling device which prevents the throughput of the packet transfer process implemented by hardware and the throughput of the packet transfer process implemented by software from affecting each other and for an auxiliary device that assists the packet receipt and transmission implemented by software.
2. Description of the Related Art
FIG. 1
illustrates the arrangement of packet transfer modules, to which the packet transfer system of the present invention is applied, in a network.
A plurality of packet transfer modules are placed in an ATM network. These packet transfer modules are connected to one another and to routers of user networks through multiplexers. The packet transfer modules, the multiplexers, and the routers are connected to one another through ATM interfaces. A packet transmitted from each of the user networks is “ATM-cellized” (in the present specification, the expression “ATM-cellized” means “assembled in a format of an ATM cell without disassembling ATM cells) by using the AAL type 5 format in the router. Then, the ATM cells transmitted from a plurality of user networks are multiplexed in the multiplexer that accommodates lines connected to a plurality of routers. Subsequently, the multiplexed ATM cells are inputted from this multiplexer to a packet transfer module.
The packet transfer module assembles the inputted ATM cells into a packet, and then retrieves a destination address from a packet header. Subsequently, the packet transfer module transmits the packet according to the destination address, which is obtained as a result of the retrieval, to a destination user network connected to a line accommodated by this transfer module itself or to another packet transfer module that accommodates a line connected to a destination user network. Meanwhile, if no destination is found as a result of the retrieval of the destination address from the packet header in the packet transfer module, this packet is terminated according to the protocol at this packet transfer module itself or, if the packet violates the protocol, the packet is not transferred but terminated at this module itself.
FIG. 2
is a diagram illustrating a principle of a conventional packet transfer system.
In this figure, reference numeral
30
designates a packet assembling/transmitting portion for receiving an ATM cell from a circuit and for transmitting an ATM cell to a circuit. Reference numeral
31
denotes a buffer memory for storing a packet to be transmitted and received. Reference numeral
32
designates a higher layer processing portion for processing header information of a packet. Reference numeral
33
denotes a processor (namely, a software processing portion) for performing software processing on a predetermined packet.
When receiving a logically multiplexed ATM cell from a circuit, the packet assembling/transmitting portion
30
disassembles the received ATM cells while the higher layer processing portion
32
retrieves a transfer destination according to a packet header and performs packet validation or verification. Then, the packet assembling/transmitting portion
30
assembles a packet and causes the buffer memory
31
to store the assembled packet. In the case that the transfer destination is determined by the higher layer processing portion
32
, the packet stored in the buffer memory
31
is assembled by the packet assembling/transmitting portion
30
into a cell without software processing performed by the processor
33
. Then, this cell is transmitted to the circuit.
Conversely, in the case that the implementation of the packet transfer process by hardware cannot be achieved because the transfer destination is not determined by the higher layer processing portion
32
, the software processing portion
33
is notified of the packet reception. Thus, the software processing portion
33
reads this packet from the buffer memory
31
and analyzes a primary factor in transfer of the packet. Consequently, the software processing portion
33
determines the next processing to be performed.
In the case that the software processing portion
33
transmits a packet, the software processing portion
33
retrieves a destination, to which the packet is to be transferred, by using a destination retrieval table
34
. Then, the software processing portion
33
writes a packet, which is to be transmitted, to the buffer memory
31
after a transfer destination is determined. Subsequently, the software processing portion
33
notifies the packet assembling/transmitting portion
30
to thereby instruct the portion
30
to transmit a packet. The packet assembling/transmitting portion
30
, which is instructed to transmit the packet, assembles the packet, which is stored in the buffer memory
31
, into a cell and then transmits this cell to the circuit. In this packet transfer system, accesses to the buffer memory
31
from the hardware (namely, the packet assembling/transmitting portion
30
) and the software (namely, the software processing portion
33
) are achieved by using the same path
35
during contention arbitration is performed.
Thus, in the case of the conventional packet transfer system, when receiving an ATM cell, a packet is assembled and stored in the buffer memory during the transfer destination retrieval and the packet validation are performed by hardware processing. In the case that the transfer destination is determined, the packet stored in the buffer memory is transmitted without software processing. Meanwhile, a packet, which needs to undergo software processing owing to the fact that the transfer destination is not determined, is received by accessing a buffer memory that is the same as the buffer memory used in the transfer implemented by hardware.
In this case, the software needs to analyze the factor that the packet is transferred, and to determine the next processing to be performed. Further, when a packet is transmitted from the software, the packet is prepared in the buffer memory and transmitted by accessing this buffer memory that is the same as a buffer memory used in the transfer implemented by the hardware. Moreover, the software needs to perform an operation of preliminarily retrieving and determining a transfer destination according to destination information of a packet.
In such a conventional packet transfer system a bus contention between an access to the buffer memory by the hardware and an access thereto by the software occurs. Thus, an increase in the number of circuits used by the software for accessing the buffer memory suppresses an access thereto by the hardware. Consequently, there has been caused a problem that the throughput of the transfer by the hard
Abe Hideo
Harada Takeshi
Tezuka Yasuo
Yamaguchi Tetsuo
Fujitsu Limited
Katten Muchin Zavis & Rosenman
Vanderpuye Kenneth
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