Packet switching network

Details Packet switching network Packet switching network

2000-01-06

2004-07-06

Vincent, David (Department: 2661)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S517000

Reexamination Certificate

active

06760346

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a packet switching network, and more particularly relates to a packet switching network in which an electric switch or an optical switch is used to carry out packet switching among multiple communication lines.
2. Description of the Related Art
A packet switching method has been widely used as a method for exchanging data in a communications network. In a communications network using a packet switching method, that is, in a packet switching network, a sending node assembles data into packets having a fixed length or a variable length, each packet having a header including a destination address of the data. The packets are sent on the network.
A packet switch in the network performs packet switching for every packet by referring to the destination address of the header thereof. A receiving node assembles packets received from the network into the original data.
An example of a packet switching network is an ATM network, which uses an asynchronous transfer mode. In the ATM network, data is transmitted in a 53-bite fixed-length packet called a cell.
Most conventional packet switches are implemented with a digital switch including electrical circuit flip-flops. Therefore, at the input port of the packet switch, bit synchronization is required to synchronize received packets to the internal clock of the packet switch. In other words, with the digital switch, when bit synchronization has been established and the switching time is sufficiently shorter than the bit interval, no bits in the packet are lost.
In the packet switch, it is necessary to perform packet synchronization after the bit synchronization has been established. Packet synchronization can be achieved by detecting the boundaries between packets. Since the switching during a packet destroys the packet, the switching must be carried out at the boundary between packets.
FIG. 1
shows an example of a conventional packet switch network using an electric digital switch. It is assumed that the packet switching network is composed of sending nodes
1
.
0
to
1
.
3
, packet switching system
300
, and receiving nodes
2
.
0
to
2
.
3
. A system clock
111
has a period equal to the bit length in a packet, and a packet clock
112
has a period equal to the packet length. The system clock
111
and the packet clock
112
are distributed to the sending nodes
1
.
0
to
1
.
3
, the packet switching system
300
, and the receiving nodes
2
.
0
to
2
.
3
.
The packet switching system
300
includes bit sync circuits
301
.
0
to
301
.
3
comprising elastic memories, a packet sync circuit
302
, and a switch
306
. The packet sync circuit
302
includes packet sync pattern detectors
303
.
0
to
303
.
3
, FIFO memories
304
.
0
to
304
.
3
, and a controller
305
.
The sending nodes
1
.
0
to
1
.
3
send packets to the packet switching system
300
, each packet having a packet sync pattern added thereto. The received packet is synchronized to the system clock
111
of the packet switching system
300
by the bit sync circuits
301
.
0
to
301
.
3
.
The bit-synchronized packet is input to a packet sync circuit
302
. When the packet sync pattern detectors
303
.
0
to
303
.
3
in the packet sync circuit
302
detect the packet synchronization pattern, they send a sync pattern detection signal to the controller
305
. The controller
305
compares the timing of the synchronization pattern detection signal received from each of the synchronization pattern detectors
303
.
0
to
303
.
3
with the timing (leading edge) of the packet clock
112
to determine the time difference between them.
The respective FIFO memories
304
.
0
to
304
.
3
of the ports receive information on the time difference obtained by the controller
305
, and then absorb the time difference by applying an appropriate delay to the corresponding packet. Since the respective head packets of all the ports are in synchronization with the packet clock
112
when output from the packet sync circuit
302
, the digital switch
306
switches at the leading edge of the packet clock
112
. In this manner, the switches are switched at the boundary of packets, so that loss of bits are avoided.
However, in the state-of-the-art of semiconductor technology, electric digital switches have a disadvantage that a clock frequency of several hundreds MHz is the maximum that allows the switch to operate. Recently, using optical transmission technology, it is possible to transmit between nodes at approximately 10 Gbps (bit/sec), but it is not possible for the electric digital switch to switch 10-Gbps serial signals as they are.
In order to increase the bit rate per port, the degree of signal parallelism must be increased. For instance, in order to achieve a per-port bit rate of 10 Gbps on condition that the switch operates at up to a clock frequency of 100 MHz, it would take one hundred 100-Mbps signals to form one port. That is, the serial signals received from the sending nodes are converted from serial to parallel, the parallel signals are exchanged at the switch, and thereafter the parallel signals are converted from parallel to serial and then the serial signals are sent to the receiving nodes. For the above reasons, there is an inevitable increase in the size and cost of the hardware.
Accordingly, in recent years, an optical packet switching method using an optical switch has come to much attention. The use of the optical packet switching method enables packets that have been sent directly as a 10-Gbit/sec serial optical signal to be switched without further alteration, whereby the hardware can be miniaturized and made inexpensive.
However, for the reasons explained below, the bit and packet synchronization methods used in the electric digital switch cannot be directly applied to an optical packet switch.
Firstly, there are no practical optical flip-flops at present. Therefore, it is not possible to use the clock of the packet switch to bring input packets in bit-sync with the clock. Since packet synchronization cannot be achieved without bit synchronization, in the conventional example, the packet synchronization cannot be obtained.
Secondly, in general, optical switches do not have a function of monitoring optical signals. Therefore, they cannot even detect a packet synchronization pattern. It is possible to monitor an optical signal by splitting a part of the optical signal. However, an optical receiver is needed to do so, consequently increasing costs.
Thirdly, as the bit rate of the signals to be switched increases, the switching time cannot be ignored with respect to the bit interval and thereby bits are likely to be erased. For instance, when the switching time is 1 nanosecond, ten bits of the 10-Gbps signal will be erased by the switching.
The above three problems may be developed not only in the optical packet switching method but also in cases such as the switching of high speed serial signals using an electric analog switch. To solve such problems, a method for providing a guard time at the boundary between packets has been proposed. For instance, in a packet communications network disclosed in Japanese Patent Application Laid-open (JP-A) No. 60-137198, a packet (a time slot in JP-A No. 60-137198) is comprised of a guard time, a preamble for synchronization, and data. At the receiving node, the preamble is used to obtain synchronization for each packet.
In the packet switch, even without bit synchronization or packet synchronization, as long as sufficient time is left for a guard time, the switching of the switch takes place within the guard time of the packet, and consequently no bits of the packet are lost.
Furthermore, Japanese Patent Application Laid-open (JP-A) No. 6-125356 discloses a synchronization circuit used in a packet communication network. At the sending side, the synchronization circuit is comprised of guard time setting means and bit-sync pattern generating means, packet-sync pattern generating means (frame synchronization in JP-A No. 6-125356). At the receivi

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