Packet switching apparatus and method in data network

Details Packet switching apparatus and method in data network Packet switching apparatus and method in data network

2000-06-12

2004-06-22

Cangialosi, Salvatore (Department: 2661)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S415000

Reexamination Certificate

active

06754222

ABSTRACT:

CLAIM OF PRIORITY
This application makes reference to and claims all benefits accruing under 35 U.S.C. Section 119 from applications for PACKET SWITCHING APPARATUS AND METHOD IN DATA NETWORK filed earlier in the Korean Industrial Property Office on Jun. 12, 1999 and Dec. 22, 1999 and there duly assigned Serial No. 21940/1999 and 60235/1999, respectively.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a packet switching system in a data network. More particularly, the present invention relates to an apparatus and method of switching packets in parallel.
2. Description of the Related Art
In all different types of networks, excluding a point-to-point network, there exists a device for data collection and distribution. A switch and a router are two of the best examples of such data collection and distribution devices. In general, a data collection and distribution device has at least two ports. The device receives data through at least one of the ports, performs the necessary data processing, and then outputs the processed data through one or more ports.
During the data collection, processing and distributing processes, congestion within the device occurs. This congestion causes latency in data transmission. The most important reason among other various reasons for such congestion is the time required for processing the data.
A conventional data packet processing method for a packet switching system operates according to the following steps:
Step
1
: a certain port receives a data packet;
Step
2
: a first-in first-out (FIFO) section temporarily stores the input data packet;
Step
3
: the input data packet waits to be processed while the previously inputted data packets are processed;
Step
4
: a data packet processing section performs the necessary process with respect to the input data packet stored in the FIFO;
After step
4
, the data processing requires a complicated decision process and this decision requires the transfer of information between decision-making modules, i.e., a controller and an information resource.
Step
5
: after the completion of the packet processing, the data packet processing section checks whether other packets previously processed exist on the corresponding output port;
Step
6
: if any other previously processed packet exists, the data packet processing section stores the processed packet in a buffer; and,
Step
7
: if the previously processed packets are all outputted, the data packet processing section transmits the processed packet stored in the buffer to the output port.
According to the conventional data packet processing method, since a single data packet processing section controls a plurality of ports and processes only one packet at a time, it can be easily implemented with a simple construction.
However, in the event that the number of input packets becomes greater with no change in the data processing time (actually, most packet switches and routers have this characteristic), the data line becomes an idle state. That is, data is not transmitted through the data line due to the delay problem in the data packet processing section. If the delay is particularly severe, data loss may occur which affects the integrity of the information.
Meanwhile, there are two elements, which should be considered in the packet processing. These elements are: (1) a control section for controlling and judging the whole processing procedure; and, (2) an information resource for storing and providing information required for the judgment of the control section. In most cases, the information resource is embodied in the form of a register and a memory. The reason that the conventional packet data processing method processes only one packet at a time in the packet switching system is because the information resource is provided using a single memory.
Accordingly, in order to solve the problems involved in the related art and to provide a rapid packet processing, the information that needs to be stored in the resource should be classified into sections or groups, so that the respective information groups are stored in different resources. Also, a plurality of transmission/reception control sections (more than the number of resources for the respective groups) should be allocated to reduce the processing overhead with respect to the input data packets.
Moreover, the transmission/reception control sections may be allocated for the respective ports. These transmission/reception control sections can reduce the control overhead and rapidly process the packets by simultaneously accessing the information resources for the respective groups.
Meanwhile, the transmission/reception control sections should be able to share the information resources. Accordingly, an arbiter or a scheduler should make the respective transmission/reception control section access one resource at a time. In case that the transmission/reception control sections access a specified information resource excessively, the access load should be maintained and balanced by readjusting the groups again.
FIG. 1
shows the construction of one embodiment known in the conventional packet switching apparatus. Referring to
FIG. 1
, a host
100
controls the whole operation of the packet switching apparatus. The host
100
takes charge of the uppermost layer and transmits commands that are inputted to the packet switching apparatus. A first MAC port
110
to the n-th MAC port
1
n
0
can be connected to another packet switching apparatus, router, or PC and perform a standard Medium Access Control (MAC) to output data packet transmission/reception commands to a transmission/reception control section
120
. A data switching section
130
determines the paths of data and control signals to the host
100
, the first MAC port
110
to the n-th MAC port
1
n
0
, and a packet memory
150
under the control of the transmission/reception control section
120
. The data switching section
130
may be implemented by a multiplexer/demultiplexer.
A search memory
140
stores information for determining an output MAC port corresponding to a destination address of the received packet, thus enables a registered MAC address to be detected. A packet memory
150
is provided with a plurality of information resources, such as an address table
152
, a port table
154
, and a packet descriptor
156
. The packet memory
150
stores the input data packets. The address table
152
stores information on the MAC address, and the port table
154
stores status information, enable information, and information upon completion of the receiving operation. The packet descriptor
156
stores information about the respective packets (for example, packet connection information) stored in the packet memory
150
.
The transmission/reception control section
120
controls the transmission/reception of packets inputted/outputted through the first MAC port
110
to the n-th MAC port
1
n
0
in accordance with the packet transmission/reception command. Specifically, the transmission/reception control section
120
temporarily stores the received data packet, checks whether the destination address of a header of the received packet is a registered address by accessing the search memory
140
, and finds out in what position of the address table
152
the registered MAC address information is stored. Then, the transmission/reception control section
120
determines the MAC port to which the received packet is outputted.
During the packet reception, the transmission/reception control section
120
stores the received data packet in the packet memory
150
by accessing the address table
152
, port table
154
, and packet descriptor
156
.
During the packet transmission, the transmission/reception control section
120
transmits the data packet stored in the packet memory
150
through the corresponding output port by accessing the address table
152
, port table
154
, and packet descriptor
156
.
FIG. 2
shows the construction of another embodiment of the conventional packet switching apparatus. Referring to
FIG. 2

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