Packet switch with centralized buffering for many output channel

Details Packet switch with centralized buffering for many output channel Packet switch with centralized buffering for many output channel

1995-02-24

1997-09-02

Ton, Dang

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370423, 370433, H04L 1256

Patent

active

056639619

ABSTRACT:
A communication network (10) includes packet switching nodes (18) in which packets from high speed data links (20, 22) are switched onto a multiplicity of low speed data links (26). Each node (18) includes a bulk RAM (30) which has a section (32) dedicated to implementing a multiplicity of logically independent FIFO buffers. A routing controller (46) controls DMA transfers of packets into and out from appropriate FIFO buffers. Packets are transferred into respective FIFO buffers consecutively and transferred out from respective FIFO buffers interleaved together.

REFERENCES:
patent: 4742446 (1988-05-01), Morioka et al.
patent: 4875206 (1989-10-01), Nichols et al.
patent: 4972315 (1990-11-01), Yamasaki et al.
patent: 5001627 (1991-03-01), Sakamoto
patent: 5023776 (1991-06-01), Gregor
patent: 5402426 (1995-03-01), Foglae et al.
patent: 5406548 (1995-04-01), Itoh et al.

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