Packet-switch system

Details Packet-switch system Packet-switch system

1999-04-29

2003-11-11

Ton, Dang (Department: 2666)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S229000, C370S395100

Reexamination Certificate

active

06647019

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the field of telecommunication and data communication systems and more particularly to the field of high speed networking systems.
2. Description of the Background of the Invention
The evolution of telecommunication (telecom) and data communication (datacom) networks has been very rapid. In particular, with telecom and datacom (i.e., network service providers) carriers continually seeking more cost-effective networks to carry greater amounts of data over existing optical fiber systems, these carriers have begun to implement high bandwidth technologies, such as wave division multiplexing (WDM) and Optical Carrier level 48c (OC-48c) (2.48 Gbps), with upwards of forty separate OC-48 channels on each optical fiber. Such telecom and datacom networks rely upon high-performance packet-switches such as large Asynchronous Transfer Mode (ATM) switches, Frame Relay switches and Internet Protocol (IP) routers.
These high-performance, high-availability (carrier-class) packet-switches typically are located in large telecom and datacom switching facilities or central offices and currently include such characteristics as: (i) an aggregate bandwidth of 40+Gbps; (ii) approximately 8-16 linecards operating at OC-48c (2.5 Gbps), which carry frames, packet-over-Synchronous Optical Network (SONET) (POS) or ATM-over-SONET; and (iii) a system availability in excess of 99.999% (i.e. out of service less than 10 minutes per year). Such packet-switches typically perform three basic functions: (i) when a data packet (cell, frame or datagram) arrives at an ingress linecard, the packet-switch decides where to transfer the data packet next (i.e. the next hop towards its destination), (ii) the packet-switch delivers the packet from the ingress linecard to the egress linecard(s) that connects to the next hop and (iii) the egress linecard decides when the data packet should be sent to its next hop (i.e. the waiting data packets could be transmitted in either a first come, first served (FCFS) order or according to a scheduling discipline that guarantees delay bounds through the packet-switch). Although the protocols used by packet-switches, such as ATM switches, Frame Relay switches and IP routers, are quite different from one another, these packet-switches still include two basic components: (1) linecards, which both terminate external lines (i.e. perform physical layer functions such as framing, clock synchronization and signaling) and determine where each data packet is to be sent next; and (2) a switch core, which transfers data packets from an ingress linecard to an egress linecard (or to multiple egress linecards if the data packet is a multicast packet).
Over the years there have been a variety of conventional architectures used for such carrier-class packet-switches. Such conventional packet-switches attempt to maximize parallelism to achieve higher performance in two particular ways. First, components that were once shared, such as centralized CPUs and shared memory, are now commonly incorporated onto each linecard where they typically support the requirements of a single interface. Second, data paths are bit-sliced to allow a stream of data packets to be processed and buffered in parallel by multiple, identical elements.
One such conventional packet-switch is built around a conventional computer architecture, as shown in FIG.
1
A: a switch core
120
, comprising a shared central (backplane) bus
150
and a central CPU/memory buffers
110
, and peripheral linecards
130
. Each linecard
130
provides the physical layer framing and interface for external lines. Data packets arriving from an external line are received by an ingress linecard
130
a
, transferred across the shared bus
150
to the central CPU/buffer module
110
, where a forwarding decision is made with regard to which egress linecard
130
z
the data packet is to be transmitted. While CPU/buffer module
110
awaits for bus
150
and the outgoing line connected to the egress linecard
130
z
to become free, the data packet is buffered; When the bus
150
and the outgoing line connected to linecard
130
z
become available, the data packet is transferred across bus
150
to egress linecard
130
z
. Linecard
130
z
then transmits the data packet out onto the external line. The main limitation of this conventional architecture is that central CPU/buffer module
110
must process every data packet, thereby limiting the throughput of such a system
100
.
This performance limitation prompted an alternative architecture as illustrated in
FIG. 1B
, where a separate CPU and memory buffer is incorporated into each linecard
160
to allow each linecard
160
to make routing decisions pertaining to egress linecard(s)
160
(e.g.
160
z
). Such parallelism of multiple processing elements increases the system performance and, by avoiding a central CPU each data packet need only traverse the bus
150
once, thereby reducing the congestion of the shared interconnect. The performance of this alternative architecture, however, is limited by the shared backplane bus
150
, which limits only one data packet at a time to traverse the bus
150
between two linecards
160
.
A more recent design, as illustrated in
FIG. 2
, attempts to overcome such an additional performance limitation by replacing the shared bus
150
with a switch core
220
. In a switch core-based architecture, multiple linecards
160
are co-located within the same rack assembly
225
as the switch core
220
as well as simultaneously communicate with one another, thereby increasing the total throughput of system
200
. A further advantage of this alternative packet-switch
200
is that the electrical connections from each linecard
160
to the switch core
220
can be short, fast, point-to-point links, rather than the previous long shared and relatively slow multi-drop links of the shared bus packet-switch
100
.
Typically, however, these conventional carrier-class packet-switches
200
only support a small number (i.e. between 8 and 16) of linecards
160
. This limited number of linecards
160
is due in part to packet-switch
200
being used as a central point for the aggregation of the bandwidth of the network. In particular, prior to reaching this aggregation point where the carrier-class packet switch
200
is located, many thousands of low-speed external lines are multiplexed together using access multiplexers and lower-speed packet-switches. To accommodate this aggregation of multiplexed line connections, the packet-switch
200
has to support ever greater aggregate bandwidth per line connection at the central aggregation point.
However, with packet-switch racks
225
within telecom and datacom central offices limited in physical size, packet-switches
200
confront packaging density limitations that limit the maximum number of linecards
160
that packet-switch
200
can include. For example, a typical central office rack size in the United States is dictated by Bellcore Networking Equipment Building Standard (NEBS), which currently is limited to 19″ wide. In addition, to ensure adequate room for air-flow for cooling between packet-switch components, such as linecards
160
, a spacing of about 1″ is needed between each linecard
160
within the packet-switch rack
225
. If such components are vertically arranged (the preferred orientation) in the packet-switch racks
225
, these practical physical constraints limit the capacity of the carrier-class packet switch
200
to approximately 16 linecards
160
per packet-switch
200
.
Unfortunately, even though the number of fibers entering each central office is not necessarily increasing, such technologies as WDM has resulted in each fiber, which is attached to the packet-switch
200
, now propagating multiple, independent high speed data packet channels, thereby requiring a larger number of linecards
160
to be included within the packet-switch
200
. For example, telecom and datacom networks are increasing the number of

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