Packet switch suitable for integrated circuit implementation

Details Packet switch suitable for integrated circuit implementation Packet switch suitable for integrated circuit implementation

1991-10-08

1993-08-03

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370 941, H04L 1256

Patent

active

052336034

ABSTRACT:
A packet switch for high-speed synchronous multiplexing of voice and picture communications collectively. The packet switch uses among other things an input multiplexer, and output demultiplexer, and a single buffer memory divided into memory areas connected to multiple input and output lines. The subdivided buffer is controlled by counters rather than a more complicated address exchanger. A second embodiment eliminates the need for an output demultiplexer because of individual read/write control of the buffer units. A third embodiment includes a bidirectional bus between an input buffer and an output buffer. A fourth embodiment uses a more economical unidirectional bus. The unidirectional bus can be limited to a part of an input packet to permit Large Scale Integration (LSI). In the LSI configuration, address filters may be replaced with a centralized address controller, and the buffer can consist of FiFo memory units or RAM units.

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A. Thomas et al., "Asynchronous Time-Division Techniques: an Experimental Packet Network Integrating Videocommunication", ISS '84, Florence, May 7-11, 1984, Session 32 C Paper 2, pp. 1, 3, 5, and 7.
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