Packet switch realizing transmission with no packet delay

Multiplex communications – Pathfinding or routing – Through a circuit switch

Reexamination Certificate

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Details

C370S394000, C370S412000, C340S002210, C379S271000

Reexamination Certificate

active

06982975

ABSTRACT:
In a packet switch structured by connecting unit switches in multi-stages which is capable of transmitting packets without delay and accommodating high-speed lines, unit switches at the first stage assign, to an input packet, a sequence number according to a destination of the packet and distribute and send out the packet to a unit switch at the succeeding stage and unit switches at the final stage sequence and output packets according to sequence numbers assigned to packets received from a unit switch at the preceding stage.

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“A Study of Control Algorithm for Large Scale ATM Switch”,Institute of Electronics, Information and Communication Engineers of Japan,Technical Study Report SSE89-173, vol. 89, No. 451, Mar. 14, 1990, pp. 61-66.

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