Packet switch device and scheduling control method

Details Packet switch device and scheduling control method Packet switch device and scheduling control method

2005-07-19

2005-07-19

Cangialosi, Salvatore (Department: 3621)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S414000, C370S415000

Reexamination Certificate

active

06920145

ABSTRACT:
A packet switch device having a plurality of input buffers; a packet switch; a plurality of schedulers, having a pipeline scheduling process module wherein a plurality of time units corresponding to the number of output lines is spent in scheduled sending process of the fixed length packets from the input buffer, and wherein the scheduled sending process is executed in a number of processes, in parallel, the number of processes corresponding to the number of the input lines, having a sending status management module wherein sending status of the fixed length packets which constitute one frame is managed for each of the input lines, and provided corresponding to any of the output lines; and at least one result notification module for notifying the input buffer of result information from the scheduled sending process performed by each of the plurality of schedulers. Further, in the scheduled sending process executed in a number of processes, in parallel, the device does not select the input line sending the fixed length packets corresponding to the same frame, and, after determining a selection, the device maintains the selection of the same input line until the completion of sending the fixed length packets corresponding to the same frame.

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McKeown, et al., “Tiny Tera: A Packet Switch Core” IEEE Micro, vol. 17, No. 1, 1997, pp. 26-33; XP000642693, ISSN:0272-1732.

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