Packet switch and buffer for storing and processing packets rout

Details Packet switch and buffer for storing and processing packets rout Packet switch and buffer for storing and processing packets rout

1994-09-19

1997-03-18

Chin, Wellington

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370428, 370395, H04J 302

Patent

active

056129521

ABSTRACT:
A packet switch has a buffer memory for storing data obtained from data packets having routing tags input from a plurality of different input ports. Plural routing tag registers store the respective routing tags in the order of input. Plural address information registers respectively corresponding to the plural routing tag registers store address information representative of a buffer memory storage region where data corresponding to the routing tags are stored. A controller searches the routing tag registers in the order of their input. A reading is made of address information stored in the address information registers corresponding to routing tags for a special output port. Data stored in the storage region of the buffer memory indicated by the address information is output to the special output port. After the routing tag registers and the address information registers corresponding to the data have been output to the output port, contents of the routing tag registers and the address information registers are shifted to the next routing tag registers and address information registers in order.

REFERENCES:
patent: 5184346 (1993-02-01), Kozaki et al.
patent: 5271004 (1993-12-01), Proctor et al.
patent: 5274641 (1993-12-01), Shobatake et al.
patent: 5280475 (1994-01-01), Yanagi et al.
patent: 5410540 (1995-04-01), Aiki et al.
"A Shared Buffer Memory Switch for an ATM Exchange", Hiroshi Kuwahara et al., Proc. ICC, pp. 118-122, (1989).
"An Efficient Self-timed Queue Architecture for ATM Switch LSI's", Harufusa Kondoh et al., IEEE 1994 Custom Integrated Circuits Conference, pp. 637-640, (1994).

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