Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2006-04-04
2006-04-04
Patel, Ajit (Department: 2664)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S415000
Reexamination Certificate
active
07023865
ABSTRACT:
A packet switch which can cyclically use α scheduling process results to determine one of M output lines as a destination of a packet stored in each of N input buffer sections by α scheduler sections independently performing scheduling processes is disclosed.
REFERENCES:
patent: 5465348 (1995-11-01), Amemiya et al.
patent: 6185188 (2001-02-01), Hasegawa
patent: 6438134 (2002-08-01), Chow et al.
patent: 6813274 (2004-11-01), Suzuki et al.
patent: 2001/0007562 (2001-07-01), Matsuoka et al.
patent: 2002/0039364 (2002-04-01), Kamiya et al.
patent: 0 569 172 (1993-11-01), None
patent: 06097965 (1994-04-01), None
patent: 200138687 (2000-05-01), None
patent: 00/64109 (2000-10-01), None
Kirstadter, “Fair and Flexible Contention Resolution for Input Buffered ATM Switches Based on LAN Medium Access Control Protocols” Broadband Communications: Global Infrastructure for the Information age. Proceedings of the International IFIP-IEEE Conference on Broadband Communications Apr. 23, 1996, XP010525736: ISBN: 0-412-75970-5; pp. 370-381.
Serpanos, et al., “High-Speed Cell Scheduling for Router Backplanes” Proceedings of the IEEE Conference 2000 on High Performance Switching and Routing. Jun. 26-29, 2000; XP001075687; ISBN: 0-7803-5884-8, pp. 65-71.
Duan, et al., “A High-Performance OC-12/OC-48 Queue Design Prototype for Input-Buffered ATM Switches” Infocom 97. Sixteenth Annual Joint Conference of the IEEE Computer and Communications Societies. Driving the Information Revolution. , Proceedings IEEE Apr. 7-11, 1997; XP010252017; ISBN: 0-8186-7780-5, pp. 20-28.
Wong, et al., “A Programmable Rate-Based Scheduler (PRS) for ATM Switches and Multiplexers” Global Telecommunications Conference, 1997. Nov. 1997; XP010254750, ISBN: 0-7803-4198-8; pp. 827-832.
Ermedahl, et al., “Response-Time Guarantees in ATM Networks” Real-Time Systems Symposium, Dec. 1997 XP010260397; ISBN: 0-8186-8268-X, pp. 274-284.
Byung Kook Kim, et al., “Scalable Hardware Earliest-Deadline-First Scheduler for ATM Switching Networks” Real-Time Systems Symposium, Dec. 1997 XP010260391, ISBN: 0-8186-8268-X, pp. 210-218.
Kawarai Kenichi
Matsuoka Naoki
Nagata Masakatsu
Tomonaga Hiroshi
Katten Muchin & Rosenman LLP
Patel Ajit
LandOfFree
Packet switch does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Packet switch, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Packet switch will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3586619