Packet striping across a parallel header processor

Details Packet striping across a parallel header processor Packet striping across a parallel header processor

2005-11-15

2005-11-15

Nguyen, Steven (Department: 2665)

Multiplex communications

Communication techniques for information carried in plural...

Assembly or disassembly of messages having address headers

C370S535000, C370S536000, C370S537000, C710S003000

Reexamination Certificate

active

06965615

ABSTRACT:
A technique is provided for striping packets across pipelines of a processing engine within a network switch. The processing engine comprises a plurality of processors arrayed as pipeline rows and columns embedded between input and output buffers of the engine. Each pipeline row or cluster includes a context memory having a plurality of window buffers of a defined size. Each packet is apportioned into fixed-sized contexts corresponding to the defined window size associated with each buffer of the context memory. The technique includes a mapping mechanism for correlating each context with a relative position within the packet, i.e., the beginning, middle and end contexts of a packet. The mapping mechanism facilitates reassembly of the packet at the output buffer, while obviating any any out-of-order issues involving the particular contexts of a packet.

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