Packet scheduler

Details Packet scheduler Packet scheduler

2006-05-16

2006-05-16

Ngo, Ricky Q. (Department: 2664)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S412000, C370S413000, C370S414000, C370S415000, C370S416000, C370S417000, C370S395400, C370S395410, C370S395420, C370S395430

Reexamination Certificate

active

07046688

ABSTRACT:
There is provided a packet scheduler for managing output awaiting packets stored in a plural of queue blocks each having a weighting coefficient settled based on an output guaranteeing bandwidth, whereby an output order for the head packets is stored in respective queue blocks. The packet scheduler includes means for controlling selection of a queue having a packet to be sent at the highest priority, based on scheduled output time information obtained by calculation using management information of the output awaiting packets and the weighting coefficient of each queue, and means for correcting processing carried out in the controlling means based on the current time information. The arrangement enables to ensure assignment of vacant bandwidth in a fair manner while suppressing erroneous operation deriving from deviation of a scheduled packet output time from the real time caused by a calculation error or the like in WFQ calculation.

REFERENCES:
patent: 6064676 (2000-05-01), Slattery et al.
patent: 6408005 (2002-06-01), Fan et al.
patent: 6469983 (2002-10-01), Narayana et al.
patent: 2005/0058149 (2005-03-01), Howe
patent: 9083525 (1997-03-01), None
patent: 10336224 (1998-12-01), None

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