Packet reassembly and deadlock avoidance for use in a packet...

Details Packet reassembly and deadlock avoidance for use in a packet... Packet reassembly and deadlock avoidance for use in a packet...

2004-06-18

2010-12-14

Vu, Huy D (Department: 2461)

Multiplex communications

Pathfinding or routing

Combined circuit switching and packet switching

C370S386000, C370S395100, C370S412000, C370S413000

Reexamination Certificate

active

07852829

ABSTRACT:
Practical packet reassembly in large, multi-plane, multi-stage switches is possible by using a scheduling technique called dynamic packet interleaving. With dynamic packet interleaving scheduling, if more than one packet is contending for the same output link in a switch module, an arbiter in the switch module gives priority to a partial packet (i.e., to a packet that has had at least one cell sent to the queue). The number of reassembly queues required to ensure reassembly is dramatically reduced (e.g., to the number of paths multiplied by the number of scheduling priorities). Deadlock may be avoided by guaranteeing (e.g., reserving) at least one cell space for all partial packets.

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