Packet processor, packet control method, and packet control...

Details Packet processor, packet control method, and packet control... Packet processor, packet control method, and packet control...

2011-08-23

2011-08-23

Duong, Frank (Department: 2474)

Multiplex communications

Pathfinding or routing

Through a circuit switch

Reexamination Certificate

active

08005078

ABSTRACT:
A packet processor having one or two or more packet processing units is provided with a packet detector which detects whether or not a packet exists in a packet processing unit, and outputs a packet detection signal indicating a result of the detection, and a clock frequency controller which controls a clock to be supplied to the packet processing unit based on the packet detection signal.

REFERENCES:
patent: 7443887 (2008-10-01), Ohkuma
patent: 7529202 (2009-05-01), Oshima
patent: 2008/0310415 (2008-12-01), Hisamatsu
patent: 2009/0268629 (2009-10-01), Hisamatsu
patent: 2009/0271647 (2009-10-01), Hisamatsu
patent: 2002164924 (2002-06-01), None
patent: 2004236350 (2004-08-01), None

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