Packet processing device implementing scheduling and...

Details Packet processing device implementing scheduling and... Packet processing device implementing scheduling and...

2005-03-11

2009-02-24

Yao, Kwang B. (Department: 2616)

Multiplex communications

Data flow congestion prevention or control

Control of data admission to the network

C370S395420

Reexamination Certificate

active

07496034

ABSTRACT:
A packet transmission device improved in packet transmission efficiency. Each packet input processor generates a pointer and identifies a packet type with respect to a received packet, and generates identification data including the pointer and the packet type identification result. A memory access controller detects a header readout amount of the packet based on the packet type identification result, generates first readout data including the header readout amount and a readout pointer indicative of a storage location of the packet in a shared memory, and adaptively reads out header data of the packet from the shared memory in accordance with the first readout data. A protocol processor analyzes the destination of the read header data, and a packet updater updates the old destination address of the packet to a new one to generate a packet with the updated destination address, and outputs the generated packet.

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