Packet processing circuit

Details Packet processing circuit Packet processing circuit

2004-03-04

2008-10-28

Yao, Kwang B. (Department: 2616)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S463000

Reexamination Certificate

active

07443887

ABSTRACT:
A packet processing circuit includes a plurality of macros and a clock supply unit. Each of the macros processes packet data on the basis of a clock and outputs the processed packet data from at least one route. The macros are cascade-connected. The clock supply unit supplies the clock to a macro to be controlled and, when no packet data is output for a predetermined time from all routes of a macro on the input side of the macro to be controlled, stops supplying the clock to the macro to be controlled.

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patent: 2006/0059377 (2006-03-01), Sherburne
patent: 2006/0259797 (2006-11-01), Fung
patent: 2001-177382 (2001-06-01), None

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