Multiplex communications – Communication techniques for information carried in plural... – Assembly or disassembly of messages having address headers
Reexamination Certificate
1999-09-17
2004-05-11
Nguyen, Steven H. D (Department: 2663)
Multiplex communications
Communication techniques for information carried in plural...
Assembly or disassembly of messages having address headers
Reexamination Certificate
active
06735219
ABSTRACT:
TECHNICAL FIELD
The present invention relates to systems, such as a packet-processing network for example, where information is transmitted by means of variable-length packet streams. It allows on-the-fly processing of packets up to very high data transmission rates.
BACKGROUND OF THE INVENTION
Packet-processing systems, like communication networks and storage systems, are getting more and more important. An advantage of this kind of packet-based systems is that each and any packet is autonomous and can be routed through a network, for example, just by making use of the information carried in the packet's header. Asynchronous transfer mode, hereinafter abbreviated to ATM, data transmission networks are well-known packet-processing systems, whereby a single processed packet has a fixed length and is called a cell. This ATM technology enables high-speed data transmission rates and supports many types of traffic, including data, facsimile, voice, video, and images, just to name some types encountered in a typical multimedia environment. The emergence of the Internet and related online technologies like teleconferencing, telemedicine, distance learning, HDTV, real-time collaboration must handle ever higher data rates. Therefore, the emphasis is on changing from switching systems for pure ATM cells to such systems supporting variable-length IP (Internet Protocol) packets in addition to ATM cells.
This patent application is related to WO 97/29613, entitled “Parallel on-the-fly Processing of Fixed Length Cells” filed on Feb. 6, 1996, presently assigned to the assignee of the instant application and the disclosure of which is incorporated herein by reference.
Typical devices for packet-processing systems of any kind are: hubs, routers, servers, switches, e.g. used for connection purposes, and adapter cards for linking computers or other devices such as printers, plotters, scanners, disk drives, fax machines, network sniffers, to a packet-processing system. The faster the packets are transmitted in such a packet-processing system, the more complex and expensive the packet-handling and -processing gets.
Some packet-processing systems have reached data transmission rates where the bounds of possibility are reached already or will be reached soon. There is a demand for new approaches to circumnavigate or solve this problem. Some networks operating in the Gigabit-per-second range have reached a stage where new solutions are needed.
It is thus an object of the present invention to provide a new concept for variable-length packet-processing even at very high data transmission rates.
It is a further object of the present invention to provide an apparatus and method enabling very fast on-the-fly processing of variable-length packets.
It is another object of the present invention to apply the approach to packet-processed systems.
It is still another object of the present invention to guarantee on-the-fly processing of variable-length packets with quality of service.
SUMMARY OF THE INVENTION
The present invention provides a packet-processing apparatus for processing an input packet stream of received variable-length packets. A variable-length packet, hereinafter simply called packet, comprises packet data and packet information, whereby the packet data is also referred to as payload, and the packet information, e.g. length, packet lifetime, header checksum, address, are usually provided in a header of the packet. A frame checksum, also referred to as FCS, can be provided at the end of an IP (Internet Protocol) packet. The packet-processing apparatus comprises a distributor for distributing the packets to several parallel and identical processing paths, whereby each path comprises at least one processing unit, whereto the packets are fed and which is able to process only for one of the packets its packet information at any moment in time. That means only one packet with packet information or in case that a packet has been interrupted into packet-parts, only one packet-part with packet information can be present for processing in one processing unit. The packet data or the packet-parts without packet information are processed by shifting them through the processing units.
The received packets may have different lengths and priorities. Further the number of clock cycles a specific unit in the processing path needs to perform its action can be larger than the length of the packet in terms of clock cycles. Hence, the next packet would arrive at this specific unit when the unit is still occupied with the previous packet. Therefore the feeding is interruptable for feeding a different of the packets to another of the parallel and identical processing paths. It is possible to interrupt the feeding of a long packet for feeding a shorter packet with a higher priority or to interrupt long packets alternately, e.g. for a well-balanced data throughput. The longer packets can be divided into several packet-parts if necessary. It is an advantage of the present invention that real-time traffic with variable-length packets can be achieved while guaranteeing on-the-fly processing of variable-length packets with quality of service, i.e. minimum delays occur during processing of variable-length packets and important packets can be processed faster.
The several packet-parts of one interrupted packet can be transmitted and processed in the same processing path through the corresponding units, which has the advantage that it is easier to collect and reassemble the packet-parts at the end of each respective processing path and because more packets can be in process during the same time. Further, it is known in which processing path and in which processing unit the packet-parts are present and it isn't thus necessary to look for the packet-parts in other processing paths.
A collector for each processing path for collecting the several packet-parts can be used at the end of each processing path, which has the advantage that the packet-parts can be collected and reassembled to the original packet before the packet is multiplexed and/or the presence of errors may be detected. The collector has preferably a buffer. Only one collector for collecting and reassembling the packet-parts from all processing paths can be applied with the advantage that chip area can be saved, collectors can be combined, resources can be shared and only one unit for collecting and reassembling is necessary.
When for each interrupted packet, information data is created, which can be an additional bit, signalizing that a packet has been interrupted, then the advantage occurs that every interrupted packet, which is divided into packet-parts, can be recognized from each processing unit, whereby for example payload can be processed faster by shifting it through the respective processing unit and no waiting for a following packet or packet-part is necessary. The collection of packet-parts at the end of the processing path using the information data allows to complete then the packet-parts back to the original packet. The additional bit can be implemented easily which is described below.
When the processing in the processing unit is operated with a predetermined clock, and the time period between two subsequently processed packets is an integer multiple of its clock cycle duration, then the advantage occurs that the processing can be carried out in a synchronized manner. Further, the clock cycles are determined and the process of the packets can be calculated in advance.
If a sorter for sorting the received packets according to their priority into priority queues is used, then the advantage occurs that a sequential packet stream is split up into several sub-streams and a fast access to the sorted packets according to their priorities is achievable.
When a selector for choosing packets from the priority queues is used, then the advantage occurs that a selection according to the priorities of the packets for further processing can be achieved and the respective selection of the packets can be carried out in an accelerated mode.
When a distributor
Beck Thomas A.
Duong Duc
Herzberg Louis
International Business Machines - Corporation
Nguyen Steven H. D
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