Multiplex communications – Pathfinding or routing – Through a circuit switch
Reexamination Certificate
1998-08-24
2001-12-25
Chin, Wellington (Department: 2664)
Multiplex communications
Pathfinding or routing
Through a circuit switch
C370S451000
Reexamination Certificate
active
06333929
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to computers, and more particularly to communications between interconnected computer nodes, storage subsystems, and other network devices.
Assessments of server and I/O technologies and their respective marketplaces make clear that cluster communications, including server-to-server communications and server-to-I/O communications, will be increasingly based on a distributed model. Existing server architectures, based on a shared-address-space model, bus-oriented connections to I/O devices and I/O transactions based on a load/store memory model, have limitations.
FIG. 1
illustrates a block diagram of a current generation computer, including CPUs
105
and
110
connected to a host bus
111
. CPU
105
is connected to a cache
106
and CPU
110
is connected to a cache
108
. The system also includes main memory
109
, and one or two host/PCI bridges
112
and
115
. Host/PCI bridges
112
,
115
convert transactions between host bus
111
and a Peripheral Component Interconnect (PCI) bus
113
. A storage controller
324
and several I/O devices
120
,
122
and
124
are connected to PCI bus
113
. I/O devices
326
are also connected to storage controller
324
.
There are limitations on the number of electrical loads which may be placed on the host bus
111
. Moreover, these configurations are also limited by the PCI bus
113
, which imposes limits both on the number of electrical loads it is capable of supporting and the physical distances at which devices can be placed. As illustrated in
FIG. 1
, storage connectivity and proximity are typically restricted to what fits within a single enclosure.
An architecture for I/O pass through of the present invention overcomes some of the disadvantages and limitations of prior art computer systems by increasing the number of I/O devices that can be connected to a computer system, by increasing the distance at which the I/O devices are located, and by permitting a more distributed architecture. The distributed computer system of the present invention increases the number of I/O devices and the distance at which they are coupled to host computers, while retaining some of the features of current I/O buses, such as PCI. However, current packet formats are impractical for usage in such a distributed computer system of the present invention. For example, the packet size used in Asynchronous Transfer Mode (ATM) is 53 bytes. However, 53 bytes is very unfriendly for use in a 32 byte cache line. Moreover, current packet formats cannot be easily used to transport host and I/O transactions without requiring significant circuitry for decoding commands or opcodes.
As a result, a need exists for an improved packet format that is more compatible with the distributed computer system of the present invention.
SUMMARY OF THE INVENTION
According to an embodiment of the present invention, a method is provided of remotely executing a bus transaction. The method includes the steps of detecting a bus transaction on a first bus located at a first node and wrapping the first bus transaction in a packet for transmission over a network. The packet includes a data field having a size that is a multiple of a cache line size. In addition, the method includes the steps of transmitting the packet over the network to the second node, unwrapping the first bus transaction from the packet received at the second node and replaying the bus transaction to the second bus for execution.
According to another embodiment of the present invention, a method is provided for transmitting a packet including information describing a bus transaction to be executed at a remote device. The method includes the steps of detecting a bus transaction on a first bus and generating a network packet describing the bus transaction. The network packet includes an opcode describing the type of transaction. One or more control signals of the bus transaction detected on the first bus map directly to one or more bits of the opcode. In addition, the method includes the steps of transmitting the packet over a network to the remote device, receiving and unwrapping the packet at the remote device and replaying the bus transaction on a second bus.
According to another embodiment of the present invention, the transmitted packet includes a header, a data field, a first CRC for the header and a second CRC for the data field. According to another embodiment, the packet includes an opcode and a transaction ID. According to yet another embodiment, the packet header includes a version field, a priority field and an address field.
REFERENCES:
patent: 5274782 (1993-12-01), Chalasani et al.
patent: 5883670 (1999-03-01), Sporer et al.
patent: 6081852 (2000-06-01), Baker
patent: 6091710 (2000-07-01), Mawhinney
patent: 6128684 (2000-10-01), Okayama
patent: 6144411 (2000-11-01), Kobayashi et al.
William Stallings, “Data and Computer Communications, ”5th Ed., 1997 Prentice Hall, pp. 435-442.
Drottar Ken
Dunning David S.
Antonelli Terry Stout & Kraus LLP
Chin Wellington
Intel Corporation
Pham Brenda H.
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