Packet disassembler for use in a control unit of an asynchronous

Multiplex communications – Wide area network – Packet switching

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Details

370 941, H04J 374, H04L 1256, H04Q 1104

Patent

active

054147026

ABSTRACT:
A packet disassembler, which eliminates the need of an upper-level processor to have an excessive processing ability, includes a plurality of fixed-length buffers having a storage capacity corresponding to a multiple of the byte length of an information field of input packets having a predetermined fixed length and each of the fixed-length buffers has an identical length. Also included in the packet disassembler is manager which, when disassembling ones of the input packets having an identical connection identifier within their headers or having a multiplexing identifier on the same connection is not completed, performs allocation control of associating the packets having the identical identifier with one of the plurality of fixed-length buffers having the identical identifier, and when the disassembling of the packets having the identical identifier is completed or when no disassembling of the packets having the identical identifier is carried out, performs allocation control of associating the associated packets with an empty one of the plurality of fixed-length buffers.

REFERENCES:
patent: 5101404 (1992-03-01), Kunimoto et al.
patent: 5113392 (1992-05-01), Takiyasu et al.
patent: 5128931 (1992-07-01), Yamanaka et al.
patent: 5173897 (1992-12-01), Schrodi et al.
patent: 5214642 (1993-05-01), Kunimoto et al.
patent: 5233606 (1993-08-01), Pashan et al.

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