Packet data analysis with efficient buffering scheme

Details Packet data analysis with efficient buffering scheme Packet data analysis with efficient buffering scheme

2005-04-19

2005-04-19

Ho, Duc (Department: 2665)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S392000, C370S417000, C370S474000, C710S052000

Reexamination Certificate

active

06882654

ABSTRACT:
Disclosed is an apparatus employing an efficient buffering scheme for analyzing the Layer 7 content in packet data sent from a first node to a second node within a computer network. The apparatus includes a first device having a buffer and one or more first processors. The apparatus also includes a second device having one or more second processors. The first device is a physically separate device from the second device. The second processor of the second device is configured to manage the buffer of the first device, and the first processor is also configured to analyze packet data accessed from the buffer.

REFERENCES:
patent: 5278834 (1994-01-01), Mazzola
patent: 5787253 (1998-07-01), McCreery et al.
patent: 6757727 (2004-06-01), Ivory

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