Packet buffer equipment

Details Packet buffer equipment Packet buffer equipment

2006-05-23

2006-05-23

Ho, Duc (Department: 2665)

Multiplex communications

Communication techniques for information carried in plural...

Assembly or disassembly of messages having address headers

C370S412000

Reexamination Certificate

active

07050461

ABSTRACT:
Packet buffer equipment in which a buffer and time for packet assembly is utilized for packet header analysis and addition processing to obtain increased efficiency. The equipment aims to receive virtual channel (VC)-multiplexed ATM cells to assemble into a packet on a VC basis maintaining each received cell, to output on a packet basis. As an embodiment, cells are assembled into a packet by storing cells from the top cell to the end cell into a packet buffer memory consisting of a plurality of cell buffers to store cells. Also, a sequence controller is provided for detecting the write completion of a new header cell, and for connecting a packet in packet-under-assembly queue constituted by under-assembly pointer into an output-wait queue.

REFERENCES:
patent: 5359600 (1994-10-01), Ueda et al.
patent: 6188689 (2001-02-01), Katsube et al.
patent: 6249528 (2001-06-01), Kothary
patent: 6728261 (2004-04-01), Sasson et al.
patent: 10-257070 (1998-09-01), None
Japanese Office Action dated Dec. 7, 2004.

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