Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1999-09-03
2003-12-02
Marcelo, Melvin (Department: 2663)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S474000, C370S395700
Reexamination Certificate
active
06658014
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims priority of Japanese Patent Application No. 11-041785 filed on Feb. 19, 1999, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a packet buffer device and a packet assembling method in a packet transfer module which assembles logical channel-multiplexed asynchronous transfer mode (ATM) cells into packets and stores and outputs the cells in packet units. More particularly, the present invention relates to a packet buffer device and a packet assembling method in a packet transfer module for a mixed network including best effort-type packet transfer services using a common buffer, and guaranteed-type packet transfer services (bandwidth guarantee) using discrete buffers.
2. Description of the Related Art
FIG. 1
is a diagram illustrating the location of network installation of packet transfer modules in an ATM network. As shown in
FIG. 1
, the packet transfer modules
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installed in the ATM network are connected to one another, and are connected to user network routers
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via multiplexing devices
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.
Individual packet transfer modules
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, multiplexing devices
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, and routers
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are connected by an asynchronous transfer mode interface. Individual packets sent from a user network are converted to ATM cells by a router
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using an ATM adaptation layer type 5 (referred to hereinafter as “AAL-type 5”) or other such protocol. The multiplexing devices
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perform multiplexing of ATM cells for multiple users and provide the multiplexed ATM cells to respective packet transfer modules
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.
The respective packet transfer modules
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assemble packets from ATM cells and transfer packets to another packet transfer module
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accommodated in a remote destination user network or to a remote destination user network accommodated in the same packet transfer module
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according to remote destination address information within a packet header.
FIG. 2
is a block diagram of a packet transfer module
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. As shown in
FIG. 2
, ATM cells multiplexed into logical channel units are input from another packet transfer module or multiplexing device to the packet transfer module
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via a circuit. A logical channel is a channel identified by a virtual channel identifier (VPI/VCI) or the like.
The packet transfer module
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includes a physical terminal device
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to perform physical layer termination of the ATM cell input/output, an ATM terminal device
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to perform ATM layer termination of ATM cell input/output, and an AAL-type 5 terminal device
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to perform AAL-type 5 termination of ATM cell input/output. The AAL-type 5 terminal device
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may also be another ATM adaptation layer-type terminal device, such as a type 3 or type 4 termination device.
A packet buffer device
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identifies an ATM cell, which is a packet end data for each logical channel, based on payload-type indication information in the ATM cell header and according to AAL-type 5 flow control or the like. The packet buffer device
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assembles a packet from ATM cells received up to that point. Packet header information including a remote destination address or the like is then output to an upper layer device
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.
The upper layer device
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searches an input packet for a transfer destination and transmits the result of the search for a transfer destination to the packet buffer device
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. The packet buffer device
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converts a transfer destination designated by the upper layer device
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to a logical channel and outputs, in packet units, ATM cells assembled into packets.
A packet transfer module controller
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performs initial setting, status control and the like of each device in the packet transfer module
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. ATM cells output from the packet transfer module
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are multiplexed into packet units and output in this form.
A conventional packet buffer device uses two types of buffering methods. One type of buffering method is to use a common buffer which stores, in a single common buffer resource, ATM cells from all subscribers to which a logical channel is assigned. Another type of buffering method is to use a conventional packet buffer device comprising discrete buffers which store ATM cells from individual subscribers in discrete buffer resources having fixed capacity previously assigned to each individual logical channel
FIG. 3
is a diagram illustrating the operation of a packet buffer device using a common buffer. As shown in
FIG. 3
, when a plurality of logical channel-multiplexed ATM cells corresponding to channels A, B, C, and D are input, the packet buffer device stores the plurality of ATM cells in packet units in a buffer memory
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which is commonly assigned to individual logical channels.
When many ATM cells corresponding to channel A are input to the common buffer memory
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so that the amount of channel A buffer memory used increases and there is insufficient empty capacity in the buffer memory
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, packets corresponding to another channel, such as channel D, are abandoned.
FIG. 4
is a diagram illustrating the operation of a packet buffer device using discrete buffers. As shown in
FIG. 4
, when a plurality of logical channel-multiplexed ATM cells corresponding to channels A, B, and C are input, the packet buffer device stores the several ATM cells in discrete buffers within a buffer memory
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, which discrete buffers are dedicated respectively to channel A, B, C, D and E use.
In a packet buffer device using discrete buffers, congestion among channels has no mutual effect. For example, as shown in
FIG. 4
, even though discrete buffers for channel D and channel E are empty, if the discrete buffers for channel A and channel B converge, packets from these channels will be abandoned.
In a packet buffer device using a common buffer, buffer processing during buffer congestion does not distinguish between packets associated with high priority, guaranteed-type transfer service, and packets associated with low-priority, best effort-type packet transfer service. Thus, it is not possible to effect abandonment processing that discriminates according to transfer service grades.
On the other hand, a packet buffer device using discrete buffers is problematic in that, if there is insufficient capacity in a certain discrete buffer resource, packets corresponding to the discrete buffer with insufficient buffer capacity are abandoned even though there is capacity in another discrete buffer resource. As a result, buffer resources are not used effectively and best effort-type packet transfer service cannot be provided with good efficiency.
Recently, ATM networks transferring Internet Protocol (IP) packets and the like have seen a transition to high speeds and high-level multiplexing, as well as a further proliferation of transfer service grades. The response to such packet transfer services requires packet buffer devices which use buffer resources optimally and which also use buffer resources selectively according to transfer service grade.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method and apparatus for dynamically constructing common buffers and discrete buffers.
Another object of the present invention is to provide a method and apparatus for optimally assigning the buffer capacity of both a common buffer type and a discrete buffer type to achieve optimal use of buffer resources.
A further object of the present invention is to provide a packet transfer service corresponding to a service mode such that packets associated with different service mode subscribers are selectively apportioned to buffers differing according to individual service mode type, even in an instance wherein the subscribers accommodated are a mixture of differing service mode subscribers.
Objects and advantages of the present invention are achieved in accordance with embodiments o
Ferris Derrick W.
Marcelo Melvin
Staas & Halsey , LLP
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