Multiplex communications – Wide area network – Packet switching
Patent
1987-04-03
1989-07-25
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
370 29, H04J 324, H04B 156
Patent
active
048520888
ABSTRACT:
A data link controller (DLC) 52 is disclosed which employs buffers (100,106) on both receive and transmit sides. These last-in, first-out buffers contain a position indicating that a character is the last one of a packet. In this way, a user need not monitor reception or transmission on a character-by-character basis, but need only concern themselves with packets. The receive and transmit FIFO's generate requests for more characters by monitoring the number of characters stored and thereby automatically receive and transmit characters without processor intervention. A four-stage mechanism (600,602,604,606,608,610,612,614) permits monitoring of multiple contiguous frames (back-to-back frames) received. Control of the DLC is provided by status and control registers (112,212) which are accessible to the user via a microprocessor interface (50). Particular registers have bit positions monitoring status conditions in such a manner that the most-probable one of a set of conditions compries the least-significant bit position, while the least-probable condition occupies the most-significant bit position. This affords simple shift and test technique for monitoring status conditions.
REFERENCES:
patent: 4016367 (1977-04-01), Law et al.
patent: 4168469 (1979-09-01), Parikh et al.
patent: 4225919 (1980-09-01), Kyu et al.
Crowe Charles
Gulick Dale E.
Lawell Terry G.
Advanced Micro Devices , Inc.
Chin Wellington
Olms Douglas W.
Salomon Kenneth B.
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