Packed word pair multiply operation forming output including mos

Details Packed word pair multiply operation forming output including mos Packed word pair multiply operation forming output including mos

1995-06-07

1997-02-25

Lall, Parshotam S.

Boots, shoes, and leggings

364754, 364736, 364DIG1, 364DIG2, G06F 744

Patent

active

056066775

ABSTRACT:
This invention is a method and apparatus for multiplication which enables two factors to be packed into the same size data word as the product. The invention partitions two N bit buses (210, 202) into a first set of M bits and a second set of L bits. In the preferred embodiment the first set of M bits is N/2 most significant bits and the second set of L bits in N/2 least significant bits. Thus N=M+L and M=L. A multiplier (220) multiplies the second sets of L bits of each of the N bit numbers. This results in a product having up to 2L bits. The invention forms an output word having a first set of L bits being the most significant L bits of the product and a second set of M bits being the first set of M bits of the first N bit data word. In the preferred embodiment, a multiplexer (221) selects between the full product of 2L bits and the packed word output. The product may be scaled prior to partitioning via a left shifter (224) which shifts the product a selected number of bit positions. The invention preferably also includes rounding the most significant half of the product using an adder (226). This invention enables multiplication of respective first and second sets of bits of a first number by respective second and third numbers, resulting in a single packed word resultant. This process includes two passes through the multiplier (220). The final resultant has a first set of bits corresponding to the most significant half of the second product and a second set of bits corresponding to the first set product from the intermediate resultant. In the preferred embodiment of this invention, the multiplier (220) is embodied in at least one digital image/graphics processor (71, 72, 73, 74) as a part of a multiprocessor (100) formed in a single integrated circuit used in image processing.

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patent: 4972362 (1990-11-01), Elkind et al.
patent: 4985861 (1991-01-01), Yamashina et al.
patent: 5128890 (1992-07-01), Givardeau, Jr.
patent: 5153848 (1992-10-01), Elkind et al.
patent: 5197140 (1993-03-01), Balmer
patent: 5293558 (1994-03-01), Narita et al.

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