Packed/add and packed subtract operations

Details Packed/add and packed subtract operations Packed/add and packed subtract operations

1996-03-04

1998-11-10

Pan, Daniel H.

Boots, shoes, and leggings

36473601, 39580036, 395306, G06F 750, G06F 1340, G11C 1114

Patent

active

058357823

ABSTRACT:
A processor having a circuit for performing a packed addition and/or packed subtraction operation. The decoder accesses the registers addressed by SRC1 and SRC2. These registers provide a first packed data and a second packed data to the circuit. Packed data consists of a number of fixed length data elements. The data elements can be eight bits, sixteen bits or thirty-two bits in length. The circuit performs the operation on the first data element from the first packed data and the first data element from second packed data, producing a first result data element. The circuit performs this operation on the next data element from the first packed data and the next data element from the second packed data, producing a next result data element. This continues for all the data elements in the first and second packed data. The result data elements constitute a result packed data that is stored in the destination register.

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