Packaging substrate structure with a semiconductor chip...

Details Packaging substrate structure with a semiconductor chip... Packaging substrate structure with a semiconductor chip...

2008-03-26

2011-10-11

Pham, Thanh V (Department: 2894)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

With housing or external electrode

C257S633000, C257S747000, C257S705000, C257SE23001, C438S107000, C438S406000

Reexamination Certificate

active

08035127

ABSTRACT:
A packaging substrate structure with a semiconductor chip embedded therein is disclosed, including a carrier board having a first and an opposed second surfaces and disposed with at least a through cavity; a semiconductor chip received in the through cavity, the chip having an active surface and an inactive surface opposite to one another, wherein the active surface has a plurality of electrode pads, a passivation layer is disposed on the active surface with the electrode pads exposed from the passivation layer, and metal pads are disposed on surfaces of the electrode pads; a buffer layer disposed on the first surface of the carrier board and on surfaces of the passivation layer and the metal pads; a first dielectric layer disposed on the buffer layer; and a first circuit layer disposed on the first dielectric layer and electrically connected with the metal pads of the chip via first conductive structures disposed in the buffer layer and the first dielectric layer, wherein the CTE (Coefficient of Thermal Expansion) of the buffer layer is between the CTE of the semiconductor chip and the CTE of the dielectric layer. Thereby, the buffer layer can reduce the stress on the interface between the dielectric layer and the semiconductor chip.

REFERENCES:
patent: 2002/0173133 (2002-11-01), Towle et al.
patent: 2006/0060984 (2006-03-01), Wakabayashi et al.
patent: 2008/0054443 (2008-03-01), Shih
patent: 2002-246501 (2002-08-01), None

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