Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2011-03-08
2011-03-08
Parekh, Nitin (Department: 2811)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C438S122000, C438S618000, C257SE23175
Reexamination Certificate
active
07901998
ABSTRACT:
A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.
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Dang Hien P.
Khanna Vijayeshwar D.
Sharma Arun
Sri-Jayantha Sri M.
International Business Machines - Corporation
Morris, Esq. Daniel P.
Parekh Nitin
Scully , Scott, Murphy & Presser, P.C.
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