Packaging substrate and semiconductor device

Details Packaging substrate and semiconductor device Packaging substrate and semiconductor device

2005-10-04

2008-10-14

Lee, Eugene (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C174S255000, C257S737000, C257S738000, C257S778000, C257S779000, C257S780000, C257SE23010, C361S767000, C361S768000

Reexamination Certificate

active

07436063

ABSTRACT:
A packaging substrate according to the present invention is a packaging substrate to which a semiconductor chip having a plurality of connection metal bodies on a surface thereof is bonded with the surface opposed to the packaging substrate and comprises a wiring provided on a bonding surface to which the semiconductor chip is bonded, a plurality of electrode parts provided on the bonding surface and electrically connected to the wiring, a wiring protective layer for coating and protecting the wiring, electrode openings formed by partly opening the wiring protective layer for separately exposing each of the electrode parts from the wiring protective layer, and escape openings each formed in continuation with each of the electrode openings in the wiring protective layer for introducing therein a part of the connection metal body to be connected to each of the electrode parts to escape.

REFERENCES:
patent: 5519580 (1996-05-01), Natarajan et al.
patent: 6028366 (2000-02-01), Abe
patent: 6201305 (2001-03-01), Darveaux et al.
patent: 6472608 (2002-10-01), Nakayama
patent: 6580174 (2003-06-01), McCormick et al.
patent: 6787443 (2004-09-01), Boggs et al.
patent: 7005750 (2006-02-01), Liu
patent: 05-047998 (1993-02-01), None

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