Packaging silicon on silicon multichip modules

Details Packaging silicon on silicon multichip modules Packaging silicon on silicon multichip modules

1998-05-19

2002-04-09

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S686000, C257S738000

Reexamination Certificate

active

06369444

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to techniques for packaging silicon interconnection substrates in multi-chip-module (MCM) assemblies.
BACKGROUND OF THE INVENTION
Use of silicon-on-silicon in premium interconnection assemblies is increasingly attractive due in part to the nearly optimum thermomechanical design made possible by the match between the Coefficient of Thermal Expansion (CTE) of the silicon chip and the silicon interconnection substrate. In state of the art silicon-on-silicon packages that provide ultra-high density, the silicon-on-silicon MCM is attached to an intermediate interconnection substrate, and the intermediate interconnection substrate is in turn mounted on a mother board. While it would seem ideal from the standpoint of thermomechanical design to construct all board levels of silicon, the size of the mother boards, and even the size of the intermediate boards, makes this option prohibitively costly. Therefore both the interconnection boards and the mother boards in multiboard assemblies are typically epoxy/glass laminates. Typical polymer laminates are not well matched thermomechanically to the silicon-on-silicon interconnection assembly. The CTE of FR-4, the most widely used epoxy laminate printed wiring board (PWB) material, is approximately 16 ppm/° C. The CTE of silicon is 2.6 ppm/° C.
An approach to reducing the thermomechanical mismatch between the silicon-on-silicon assembly and the intermediate board would appear to be to construct the intermediate board of a plastic material that matches the CTE of silicon. However, the shortcoming of this approach is that the mismatch between the intermediate board and the conventional mother board is then unacceptable.
Solder bond interlevel interconnections, i.e. those between interconnection substrates, are known to deform plastically, and the lifetime limitation due to thermal fatigue of solder interconnections is known to proceed as the square of the strain in the interconnection. Therefore a reduction in differential expansion of relatively small proportions can be expected to have a significant impact on the useful lifetime of multiple board interconnection assemblies.
SUMMARY OF THE INVENTION
We have designed a silicon-on-silicon interconnection package that overcomes the deficiencies of the interconnection packages described above. In the package of the invention both the intermediate interconnection board and the mother board have a CTE that closely matches the CTE of silicon. The preferred embodiment of the invention is a PC card in which the problem of thermomechanical incompatibility between the intermediate interconnection substrate, with a modified CTE, and the mother board is eliminated. This arrangement allows total design freedom to optimize the thermomechanical compatibility between the silicon-on-silicon multi-chip module and the PWB of the PC card, and eliminates the problem of CTE mismatch between silicon and conventional epoxy laminate boards. In this package design strain of solder interconnections due to mismatch in CTE between the materials of adjacent board levels is largely eliminated and the lifetime of the solder interconnections is substantially improved. The assembly of the invention offers the additional advantage of allowing single silicon flip-chips to be surface mounted directly to the intermediate board level without significant CTE mismatch.


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