Packaging of hybrid integrated circuits

Details Packaging of hybrid integrated circuits Packaging of hybrid integrated circuits

2007-06-18

2008-12-23

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S777000, C438S107000, C438S108000

Reexamination Certificate

active

07468556

ABSTRACT:
Improved sensor packaging is provided with a hybrid integration approach. In one example, an application specific integrated circuit (ASIC) for sensor signal conditioning is packaged. The ASIC package has an aperture in it that exposes a chip to chip bonding interface of the ASIC chip. The rest of the ASIC chip is surrounded by the package, including the connections between the external package leads and the ASIC chip. A sensor chip, also having a chip to chip bonding interface, is disposed in the package aperture and bonded to the ASIC chip such that the two chip to chip bonding interfaces are connected. Flip chip bonding of the sensor chip to the ASIC chip is a preferred approach for chip to chip bonding. The vertical gap between the two chips can be filled in by an underfill process. The lateral gap between the sensor chip and the package can also be filled.

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