Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With structure for mounting semiconductor chip to lead frame
Reexamination Certificate
2000-06-02
2003-02-18
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With structure for mounting semiconductor chip to lead frame
C257S666000, C257S692000, C257S735000, C257S696000, C257S698000, C257S712000, C257S717000, C257S673000, C257S401000, C257S329000, C257S139000, C257S341000, C257S675000
Reexamination Certificate
active
06521982
ABSTRACT:
BACKGROUND
1. Technical Field
This invention relates to packaging of semiconductor devices in general, and in particular, to a method and apparatus for reliably connecting the die of a high power semiconductor device, such as a power MOSFET, IGBT, rectifier, or SCR device, to an associated substrate with a conductive strap.
2. Related Art
Some high power semiconductor devices are fabricated by forming a number of individual, lower power devices in a single semiconductor die, or “chip,” then connecting the individual devices together in parallel within the package of the device to define a single device capable of higher power output.
Thus, in an exemplary eight-lead, standard outline integrated circuit (“SOIC-8”) high-power, metal-oxide-semiconductor field effect transistor (“PMOSFET”) device, the sources of the individual devices are all located on the top of the die, and are connected in parallel by a thin layer of metal on the top of the die, which in turn, is internally connected to each of three leads of the device.
In prior art versions of this type of device, the sources of the individual MOSFETs were connected to the substrate of the device by a relatively large number (typically,14) of parallel bonded wires. However, these wires contributed to a number of problems associated with this type of device, including relatively high internal thermal and electrical resistances, high parasitic source-inductance, and the formation of craters and Kirkendall voids in the die caused by the bonding of the wires.
More recently, it has been learned that most of the foregoing problems can be eliminated or reduced by replacing the large number of bonded wires from the source of the device with a single, elongated conductive strap that connects the thin layer of metal on top of the die to the source leads of the substrate. (See, e.g., U.S. Pat. No. 6,040,626 to C. Cheah, et al.; see also, Patrick Manion, “MOSFETs Break Out Of The Shackles of Wirebonding,”
Electronic Design,
Mar. 22, 1999, Vol. 47, No. 6.)
However, this latter method of connecting the die to the substrate has also been found to have some problems associated with it. One of these relates to the differences in the respective thermal coefficients expansion (“TCE”) of the materials of the strap, die, and substrate. As a result of these differences, these parts respectively experience different amounts of expansion and contraction with changes in the temperature of the device. This relative movement of the respective parts causes large shear stresses to develop in the attachment joints between them, which are typically lap joints of conductive adhesive or solder. These shear stresses result in a degradation of the electrical connection between the strap, die, and substrate, and in particular, in an unacceptably large change, or “shift,” in the critical drain-to-source resistance of the device when it is on (R
DS(ON)
).
A need therefore exists for a method and apparatus for reliably connecting the dies of a variety of high power semiconductor devices to a substrate with a conductive strap such that the electrical connections between the parts are immune to the destructive effects of temperature-induced stresses in the connections.
BRIEF SUMMARY
This invention provides a method and apparatus for packaging a high power semiconductor device, such as a high power MOSFET, an insulated gate bipolar transistor (“IGBT,” or “JFET”), a silicon controlled rectifier (“SCR,” or “triac”), a bipolar junction transistor (“BJT”), or a diode rectifier, in which the die of the device is connected, electrically and thermally, to a substrate on which the die is mounted, e.g., a lead frame, with a conductive strap, such that the connection is more resistant to the shear stresses incident upon it with changes in temperature of the device. The enhanced reliability of this connection, in turn, enhances overall device reliability and reduces semiconductor device failures due to, e.g., large changes in the device's R
DS(ON)
parameter.
The method includes the provision of a semiconductor die, an interconnective substrate, and a conductive metal strap. The substrate has a first portion with a first lead connected thereto, and a second portion with a second lead connected thereto. The first and second portions of the substrate are electrically isolated from each other.
The die has top and bottom surfaces and at least one active electronic device, e.g., a MOSFET, an IGBT, a BJT, an SCR, or a rectifier, formed therein. The active device has a first terminal, e.g., a source, emitter, or anode terminal, connected to a first electrically conductive layer on the bottom surface of the die, and a second terminal, e.g., an associated drain, collector, or cathode terminal, connected to a second conductive layer on the top surface of the die. The first conductive layer is attached to a top surface of the first portion of the substrate by a first joint of an electrically conductive material. The device may also have a gate terminal connected to a third conductive layer, or gate pad, on the bottom surface of the die, which is electrically isolated from the first conductive layer thereon. The gate pad is attached to a top surface of an inner end of a third lead that is associated with, but electrically isolated from, the first portion of the substrate and first lead connected thereto.
The conductive strap has a cover portion, a down-set portion at an edge of the cover portion, and a flange portion at an edge of the down-set portion. The cover portion is attached to the second conductive layer on the top surface of the die with a second joint of an electrically conductive material, and the flange portion is attached to a top surface of the second portion of the substrate with a third joint of an electrically conductive material.
In one embodiment, a recess is formed in the top surface of the second portion of the substrate. The recess has a floor disposed below the top surface of the substrate. The recess captivates the flange portion of the strap and prevents movement of the flange relative to the substrate with variations in device temperature.
A better understanding of the above and other features and advantages of the present invention may be obtained from a consideration of the detailed description of its exemplary embodiments found below, particularly if such consideration is made in conjunction with the several views of the drawings appended hereto.
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http://www.siliconix.com, “New Package Technology Yields Nearly Twofold Improvement Over Previous State of the Art,” Vishey Siliconix Press Release, Dec. 9, 1998.
Internet Website Article, Electronic Design—Mar. 22, 1999, vol. 47, No. 6-MOSFETs Break Out of The Shackles Of Wirebonding.
File Wrapper for Provisional patent application No. 60/101810.
Boland Bradley D.
Crowley Sean T.
Gillett Blake A.
Amkor Technology Inc.
Parsons James E.
Skjerven Morrill LLP
Williams Alexander O.
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