Packaging design system for an LSI circuit

Details Packaging design system for an LSI circuit Packaging design system for an LSI circuit

1996-06-25

1999-04-06

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364491, G06F 1700, G06F 1750

Patent

active

058926852

ABSTRACT:
A packaging design system for an LSI circuit includes: a gate placement preparation unit for preparing basic placement data for gates used as an original data for producting the LSI circuit; a wiring data preparation unit operatively connected to the gate placement preparation unit for preparing wiring data based on wiring patterns each having the same length between gates; a delay calculation unit operatively connected to the wiring data preparation unit for calculating net delays between gates and path delays from a clock input until an output in the LSI circuit; a standard path delay determining unit operatively connected to the delay calculation unit for determining a standard path delay in accordance with distribution of path delays; and a macro determining unit operatively connected to the standard path delay determining unit for selecting the macros in accordance with predetermined conditions of path delays, and selected several macros being used for an actual placement of gates.

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