Packages for electronic devices implemented with laminated...

Details Packages for electronic devices implemented with laminated... Packages for electronic devices implemented with laminated...

2005-09-07

2010-11-23

Fahmy, Wael M (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S737000, C257S738000, C257S687000, C257S688000, C257S690000, C257S790000, C257S792000, C257S795000, C257SE23001, C257SE23194, C257SE23021, C257SE23069, C257SE21508

Reexamination Certificate

active

07838977

ABSTRACT:
This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

REFERENCES:
patent: 6137164 (2000-10-01), Yew et al.
patent: 6815254 (2004-11-01), Mistry et al.
patent: 7205647 (2007-04-01), Karnezos
patent: 2001/0028114 (2001-10-01), Hosomi
patent: 2004/0178508 (2004-09-01), Nishimura et al.
patent: 2005/0087854 (2005-04-01), Choi et al.

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