Packaged stacked semiconductor die and method of preparing same

Details Packaged stacked semiconductor die and method of preparing same Packaged stacked semiconductor die and method of preparing same

2001-10-10

2003-02-04

Paladini, Albert W. (Department: 2827)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S460000, C438S464000, C438S109000, C438S114000

Reexamination Certificate

active

06514795

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor packaging technology, and, more particularly, to a packaged stacked semiconductor die and a method of preparing same.
2. Description of the Related Art
Integrated circuit devices proceed through a complicated and time-consuming fabrication routine before being completed and ready for packaging. Once an integrated circuit device passes final inspection, it is passed to packaging. The integrated circuit device (IC) then is typically encapsulated in a protective package made of plastic, metal, ceramic material, or combinations thereof. The package is sealed to insulate the semiconductor die from the effects of temperature extremes, humidity and unintentional electrical contacts. The package has a plurality of conductive leads protruding from the encapsulation material for connecting to external devices on a printed circuit board. Various types of semiconductor packages include sealed metal cans, plastic and ceramic dual in-line packages, small outlining packages, single in-line packages, surface mount packages, and various other flat packages.
There is a need to increase the semiconductor die density of a semiconductor package to include two or more semiconductor dice in one package. A high density package, having multiple semiconductor die therein, increases the electronic component density on a printed circuit board. Such a high density semiconductor package also maximizes space utilization on a printed circuit board and further increases the number of active elements on the printed circuit board.
In such stacked die arrangements, particularly of die of approximately the same size, there must be sufficient clearance between the top surface of the bottom die and the bottom surface of the top die for the wire bonds affixed to bonding pads on the top of the bottom die. For example, in some prior art packaging techniques, a spacer comprised of an adhesive-type material is positioned between the top and bottom die. The spacer has a thickness sufficient to provide the necessary mechanical clearance, e.g., 75-175 &mgr;m, for the wire bonds coupled to the bottom die. The spacer is sized such that it does not cover any of the bonding pads on the top surface of the bottom die. That is, the spacer has a surface area that is less than the surface area of the die it is positioned between. Accordingly, sufficient mechanical clearance is provided for the wire bonds on the bottom die due to the reduced size of the spacer and its thickness. Alternatively, a similar type spacer comprised of silicon may be positioned between the top die and bottom die and attached to each of them with an adhesive paste. However, given the constant drive to increase manufacturing efficiencies, a need exists for a more efficient stacked die packaging apparatus and method.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems described above.
SUMMARY OF THE INVENTION
In general, the present invention is directed to a method for packaging stacked die. In one illustrative embodiment, a method disclosed herein comprises providing a section of wafer mount tape, applying an adhesive layer to the wafer mount tape, stretching the wafer mount tape and the adhesive layer, attaching a wafer to the stretched adhesive layer, cutting the wafer and the adhesive layer, the wafer being cut into a plurality of die, and curing the wafer mount tape. In further embodiments, the method comprises removing at least one of the plurality of die from the wafer mount tape, the removed die having a portion of the adhesive layer coupled thereto, providing a die having a plurality of wire bonds coupled thereto, and coupling the adhesive layer on the removed die to the die having the wire bonds coupled thereto.
In another aspect, the present invention is directed to a plurality of stacked semiconductor devices that comprise a first die, the first die having an upper surface, a second die positioned above the first die, the second die having a bottom surface, and an adhesive layer positioned between and coupled to each of the first die and the second die, the adhesive layer comprised of first and second surfaces, the first surface of the adhesive layer being coupled to the bottom surface of the second die thereby defining a first contact area, the second surface of the adhesive layer being coupled to the upper surface of the first die thereby defining a second contact area, the second contact area being less than the first contact area. In further embodiments, the second surface of the adhesive layer has a lateral dimension that is less than a lateral dimension of the first surface of the adhesive layer.


REFERENCES:
patent: 5411921 (1995-05-01), Negoro
patent: 5882956 (1999-03-01), Umehara et al.

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