Packaged semiconductor substrate

Details Packaged semiconductor substrate Packaged semiconductor substrate

1999-01-08

2001-06-26

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Encapsulated

C257S729000

Reexamination Certificate

active

06252309

ABSTRACT:

BACKGROUND OF THE INVENTION
1 Field of the Invention
The present invention relates to a packaged semiconductor substrate, and more particularly to a degatable electrically insulating layer provided between the position for pouring the package encapsulant and the substrate to prevent direct contact between the package encapsulant and the substrate surface at the position for pouring the package encapsulant during manufacture of a substrate for a ball grid array integrated circuit (BGA IC).
2. Description of the Related Art
Conventional quad flat pack (QFP) and pin-grid array (PGA) methods for packaging integrated circuits cannot meet practical needs as the functions of integrated circuits have become more and more complicated while the integration level of the circuits become higher and higher. Ball grid array integrated circuit (BGA IC) packaging method is one of the newly developed methods for ICs with a quantity of pins and is suitable for packaging ultra-large scale integration (ULSI) produced by submicron solution.
Referring to
FIG. 1A
, when proceeding with plastic BGA packaging that is common in BGA ICs, a mold (not shown) is put on top of the substrate
11
of a BGA IC (an electronic device
10
to be packaged), and molten liquid plastic material (i.e., a package encapsulant) is then poured into the mold to completely enclose the integrated circuits on the substrate
11
to thereby provide a completely air tight seal for the integrated circuit chips. Referring to
FIG. 1B
, the BGA IC (the packaged electronic device
10
) is removed from the mold after the plastic material is hardened. Subsequent trim work is carried out on an area adjacent a mold gate (not shown) of the mold to remove the residual plastic material in a pouring channel (not shown) of the mold. In the above-mentioned packaging method for BGA ICs, a metallic plate
13
(
FIG. 2
) is provided on the substrate
11
and includes a metallic surface formed by depositing gold on a side thereof. When the substrate is covered by the mold, the metallic surface is located below the pouring channel of the mold. The metallic surface serves as an isolating layer between the substrate and the pouring channel during pouring of the package encapsulant, thereby providing an increased degating ability. More specifically, when removing the substrate from the mold, the metallic surface allows the residual package encapsulant in the pouring channel to be easily degated from the substrate. Thus, the residual on the packaged IC can be easily trimmed. Nevertheless, in addition to an increased cost as a result of using gold, the metallic plate occupies a certain space and thus reduces the space available for layout. Furthermore, as shown in
FIG. 2
, when the metallic plate
13
is expanded as a result of heat, the solder masks
15
on both sides of the metallic plate
13
are squeezed in the lateral direction such that the layout
14
in each solder mask
15
is also squeezed. As a result, the product defective index is increased.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a packaged semi-conductor substrate without the conventional mold gate. A film is mounted in the package encapsulant position to form a layer that is degatable along with the pouring channel. As a result, the film and the package encapsulant will not be residual on the substrate. The substrate of the present invention may increase the space available for the layout and lower manufacturing cost as no gold is required. Thus, a crowded layout on the substrate is avoided and the product defective index is lowered. In addition, the degating ability between the position for pouring the package encapsulant and the package encapsulant is not affected.
In accordance with the present invention, the substrate includes a film provided to the position for pouring package encapsulant. The film has an adhesive force so as to be adhered to the position for pouring package encapsulant. The layout is located below the film, while a layer of solder mask is deposited on the layout. When the package encapsulant is poured into the position for pouring package encapsulant, the package encapsulant does not directly contact with the solder mask by means of an isolation effect provided by the film. In this case, an adhering force is generated between the package encapsulant in the pouring channel and the film such that the film can be adhered to the package encapsulant in the pouring channel. An adhering force between the film and the package encapsulant is greater than an adhering force between the film and the mask such that the film is degated along with the package encapsulant in the pouring channel during a degating procedure of the pouring channel after a pouring procedure of the package encapsulant. Thus, the film and the package encapsulant are not residual on the substrate.
Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5635671 (1997-06-01), Freyman et al.
patent: 5886398 (1999-03-01), Low et al.

Affiliated with

Also associated with

Rating

Packaged semiconductor substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Packaged semiconductor substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Packaged semiconductor substrate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2496925