Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2002-08-21
2004-05-25
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C438S112000
Reexamination Certificate
active
06740546
ABSTRACT:
TECHNICAL FIELD
The present invention is related to packaged microelectronic devices and methods for assembling microelectronic devices.
BACKGROUND
Microelectronic devices generally have a die (i.e., a chip) that includes integrated circuitry having a high density of very small components. In a typical process, a large number of dies are manufactured on a single wafer using many different processes that may be repeated at various stages (e.g., implanting, doping, photolithography, chemical vapor deposition, plasma vapor deposition, plating, planarizing, etching, etc.). The dies typically include an array of very small bond-pads electrically coupled to the integrated circuitry. The bond-pads are the external electrical contacts on the die through which the supply voltage, signals, etc., are transmitted to and from the integrated circuitry. The dies are then separated from one another (i.e., singulated) by dicing the wafer and backgrinding the individual dies. After the dies have been singulated, they are typically “packaged” to couple the bond-pads to a larger array of electrical terminals that can be more easily coupled to the various power supply lines, signal lines and ground lines.
An individual die can be packaged by electrically coupling the bond-pads on the die to arrays of pins, ball-pads, or other types of electrical terminals, and then encapsulating the die to protect it from environmental factors (e.g., moisture, particulates, static electricity and physical impact). In one application, the bond-pads are electrically connected to contacts on an interposer substrate that has an array of ball-pads.
FIG. 1
schematically illustrates a packaged microelectronic device
10
including an interposer substrate
20
and a microelectronic die
40
attached to the interposer substrate
20
. The microelectronic die
40
has been encapsulated with a casing
70
to protect the die
40
from environmental factors.
One drawback of encapsulating the microelectronic die
40
is the bowing or warpage of the interposer substrate
20
that occurs after the casing
70
cools. The bowing is caused by the difference between the coefficients of thermal expansion of the interposer substrate
20
, the microelectronic die
40
, and the casing
70
. The warpage of the interposer substrate
20
can create sufficient stress to cause failure in the solder links between the interposer substrate
20
and a printed circuit board to which the interposer substrate
20
is attached. Accordingly, there is a need to reduce and/or eliminate the warpage in the microelectronic device
10
.
Moreover, electronic products require packaged microelectronic devices to have an extremely high density of components in a very limited space. For example, the space available for memory devices, processors, displays and other microelectronic components is quite limited in cell phones, PDAs, portable computers and many other products. As such, there is a strong drive to reduce the height of the packaged microelectronic device
10
and the surface area or “footprint” of the microelectronic device
10
on a printed circuit board. Reducing the size of the microelectronic device
10
is difficult because high performance microelectronic devices
10
generally have more bond-pads, which result in larger ball-grid arrays and thus larger footprints. One technique used to increase the density of microelectronic devices
10
within a given footprint is to stack one microelectronic device
10
on top of another.
FIG. 2
schematically illustrates the packaged microelectronic device (identified as
10
a
) of
FIG. 1
stacked on top of a second similar microelectronic device
10
b
. The interposer substrate
20
of the first microelectronic device
10
a
is coupled to the interposer substrate
20
of the second microelectronic device
10
b
by large solder balls
80
. The large solder balls
80
required to span the distance between the two interposer substrates
20
use valuable space on the interposer substrates
20
, and thus increase the footprint of the microelectronic devices
10
. Accordingly, there is a need to reduce the footprints of stacked microelectronic devices
10
.
SUMMARY
The present invention is directed to packaged microelectronic devices and methods for assembling microelectronic devices. One aspect of the invention is directed to a method of packaging a microelectronic device including a die having an integrated circuit and an interposer substrate having a ball-pad electrically coupled to the integrated circuit. In one embodiment, the method includes depositing a solder ball onto the ball-pad and molding a compound to form a casing around at least a portion of the die and at least a portion of the solder ball. In a further aspect of this embodiment, the method can further include forming a first cover over a first surface of the interposer substrate with the compound and forming a second cover over a second surface opposite the first surface of the interposer substrate with the compound. The first cover can have a first volume and the second cover can have a second volume at least approximately equal to the first volume. In another aspect of this embodiment, the first cover can have a first surface area and the second cover can have a second surface area at least approximately equal to the first surface area.
In another embodiment of the invention, the method includes placing the solder ball onto the ball-pad and encapsulating the die and the first and second surfaces of the interposer substrate to form the first cover over the first surface and the second cover over the second surface. In a further aspect of this embodiment, the first cover can have a first surface area and the second cover can have a second surface area at least approximately equal to the first surface area. In another aspect of this embodiment, the first cover can have a first volume and the second cover can have a second volume at least approximately equal to the first volume. In further aspect of this embodiment, placing the solder ball occurs before encapsulating the die and the first and second surfaces.
In another embodiment of the invention, a packaged microelectronic device includes a microelectronic die having an integrated circuit and a bond-pad coupled to the integrated circuit and an interposer substrate coupled to the die. The interposer substrate has a first surface, a second surface opposite the first surface, and a ball-pad electrically coupled to the bond-pad on the die. The microelectronic device also includes a solder ball on the ball-pad and a casing covering the die, at least a portion of the first surface, and at least a portion of the second surface. In a further aspect of this embodiment, the casing can cover at least a portion of the solder ball. In another aspect of this embodiment, the casing includes a first cover and a second cover. The first cover has a first surface area and a first volume, and the second cover has a second surface area and a second volume. The first surface area can be at least approximately equal to the second surface area, and the first volume can be at least approximately equal to the second volume.
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Brooks Mike
Corisis David J.
Geyer Scott B.
Micro)n Technology, Inc.
Perkins Coie LLP
Pert Evan
LandOfFree
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